| Copy or discard execution model for speculative parallelization on multicores C Tian, M Feng, V Nagarajan, R Gupta 2008 41st IEEE/ACM International Symposium on Microarchitecture, 330-341, 2008 | 173 | 2008 |
| Atom: Atomic durability in non-volatile memory through hardware logging A Joshi, V Nagarajan, S Viglas, M Cintra 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 148 | 2017 |
| Efficient persist barriers for multicores A Joshi, V Nagarajan, M Cintra, S Viglas Proceedings of the 48th International Symposium on Microarchitecture, 660-671, 2015 | 148 | 2015 |
| ATCache: Reducing DRAM cache latency via a small SRAM tag cache CC Huang, V Nagarajan Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 129 | 2014 |
| A primer on memory consistency and cache coherence V Nagarajan, DJ Sorin, MD Hill, DA Wood Springer Nature, 2020 | 98 | 2020 |
| TSO-CC: Consistency directed cache coherence for TSO M Elver, V Nagarajan 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 79 | 2014 |
| Hermes: A fast, fault-tolerant and linearizable replication protocol A Katsarakis, V Gavrielatos, MRS Katebzadeh, A Joshi, A Dragojevic, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 74 | 2020 |
| Blasting through the front-end bottleneck with shotgun R Kumar, B Grot, V Nagarajan ACM SIGPLAN Notices 53 (2), 30-42, 2018 | 72 | 2018 |
| Dynamic recognition of synchronization operations for improved data race detection C Tian, V Nagarajan, R Gupta, S Tallam Proceedings of the 2008 international symposium on Software testing and …, 2008 | 72 | 2008 |
| Dhtm: Durable hardware transactional memory A Joshi, V Nagarajan, M Cintra, S Viglas 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 71 | 2018 |
| Boomerang: A metadata-free architecture for control flow delivery R Kumar, CC Huang, B Grot, V Nagarajan 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 70 | 2017 |
| Efficient sequential consistency via conflict ordering C Lin, V Nagarajan, R Gupta, B Rajaram ACM SIGPLAN Notices 47 (4), 273-286, 2012 | 62 | 2012 |
| Efficient sequential consistency using conditional fences C Lin, V Nagarajan, R Gupta Proceedings of the 19th international conference on Parallel architectures …, 2010 | 56 | 2010 |
| Dynamic information flow tracking on multicores V Nagarajan, HS Kim, Y Wu, R Gupta Workshop on Interaction between Compilers and Computer Architectures …, 2008 | 54 | 2008 |
| Matching control flow of program versions V Nagarajan, R Gupta, X Zhang, M Madou, B De Sutter, K De Bosschere 2007 IEEE International Conference on Software Maintenance, 84-93, 2007 | 49 | 2007 |
| Avocado: A Secure {In-Memory} Distributed Storage System M Bailleu, D Giantsidi, V Gavrielatos, V Nagarajan, P Bhatotia 2021 USENIX Annual Technical Conference (USENIX ATC 21), 65-79, 2021 | 48 | 2021 |
| McVerSi: A test generation framework for fast memory consistency verification in simulation M Elver, V Nagarajan 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 45 | 2016 |
| ECMon: exposing cache events for monitoring V Nagarajan, R Gupta ACM SIGARCH Computer Architecture News 37 (3), 349-360, 2009 | 45 | 2009 |
| Architectural support for shadow memory in multiprocessors V Nagarajan, R Gupta Proceedings of the 2009 ACM SIGPLAN/SIGOPS international conference on …, 2009 | 44 | 2009 |
| Scale-out ccNUMA: Exploiting skew with strongly consistent caching V Gavrielatos, A Katsarakis, A Joshi, N Oswald, B Grot, V Nagarajan Proceedings of the Thirteenth EuroSys Conference, 1-15, 2018 | 41 | 2018 |
