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Deog-Kyoon Jeong
Deog-Kyoon Jeong
Seoul National University, Department of Electrical and Computer Engineering
Zweryfikowany adres z snu.ac.kr - Strona główna
Tytuł
Cytowane przez
Cytowane przez
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An efficient charge recovery logic circuit
Y Moon, DK Jeong
IEEE Journal of Solid-State Circuits 31 (4), 514-522, 1996
6661996
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
Y Moon, J Choi, K Lee, DK Jeong, MK Kim
IEEE Journal of Solid-State Circuits 35 (3), 377-384, 2000
3052000
System and method for sending multiple data signals over a serial link
S Kim, DD Lee, DK Jeong
US Patent 5,835,498, 1998
2871998
Design of PLL-based clock generation circuits
DK Jeong, G Borriello, DA Hodges, RH Katz
IEEE Journal of Solid-State Circuits 22 (2), 255-261, 1987
2441987
A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
JS Choi, MS Hwang, DK Jeong
IEEE Journal of Solid-State Circuits 39 (3), 419-425, 2004
1842004
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
S Kim, K Lee, Y Moon, DK Jeong, Y Choi, HK Lim
IEEE Journal of Solid-state circuits 32 (5), 691-700, 1997
1741997
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS-and cellular-CDMA wireless systems
Y Koo, H Huh, Y Cho, J Lee, J Park, K Lee, DK Jeong, W Kim
IEEE Journal of Solid-State Circuits 37 (5), 536-542, 2002
1472002
A CMOS serial link for fully duplexed data communication
K Lee, S Kim, G Ahn, DK Jeong
IEEE Journal of Solid-State Circuits 30 (4), 353-364, 1995
1351995
Reduction of pump current mismatch in charge-pump PLL
MS Hwang, J Kim, DK Jeong
Electronics letters 45 (3), 135-136, 2009
1292009
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver
KY Lee, SW Lee, Y Koo, HK Huh, HY Nam, JW Lee, J Park, K Lee, ...
IEEE Journal of Solid-State Circuits 38 (1), 43-53, 2003
1242003
High speed serial link for fully duplexed data communication
DK Jeong
US Patent 5,675,584, 1997
1161997
A practical implementation of IEEE 1588-2008 transparent clock for distributed measurement and control systems
J Han, DK Jeong
IEEE transactions on instrumentation and measurement 59 (2), 433-439, 2009
1092009
A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS
HR Lee, O Kim, G Ahn, DK Jeong
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
1052005
Single chip CMOS transmitter/receiver and method of using same
K Lee, DK Jeong, J Park, W Kim
US Patent 6,781,424, 2004
992004
Multi-gigabit-rate clock and data recovery based on blind oversampling
J Kim, DK Jeong
IEEE Communications Magazine 41 (12), 68-74, 2003
982003
A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS
J Kim, JK Kim, BJ Lee, N Kim, DK Jeong, W Kim
IEEE Journal of Solid-State Circuits 41 (4), 899-908, 2006
962006
Multisection memory bank system
D Lee, Y Shin, DD Lee, DK Jeong, S Kong
US Patent 7,340,558, 2008
922008
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
SH Lee, MS Hwang, Y Choi, S Kim, Y Moon, BJ Lee, DK Jeong, W Kim, ...
IEEE Journal of Solid-State Circuits 37 (12), 1822-1830, 2002
912002
Data recovery using data eye tracking
S Lee, DK Jeong
US Patent App. 09/943,029, 2002
87*2002
Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s
G Kim, JW Park, IG Kim, S Kim, S Kim, JM Lee, GS Park, J Joo, KS Jang, ...
Optics Express 19 (27), 26936-26947, 2011
862011
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