| Reliability aware NoC router architecture using input channel buffer sharing MH Neishaburi, Z Zilic Proceedings of the 19th ACM Great Lakes symposium on VLSI, 511-516, 2009 | 61 | 2009 |
| An efficent dynamic multicast routing protocol for distributing traffic in NOCs M Ebrahimi, M Daneshtalab, MH Neishaburi, S Mohammadi, ... 2009 Design, Automation & Test in Europe Conference & Exhibition, 1064-1069, 2009 | 33 | 2009 |
| ERAVC: Enhanced reliability aware NoC router MH Neishaburi, Z Zilic 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 28 | 2011 |
| Enabling efficient post-silicon debug by clustering of hardware-assertions MH Neishaburi, Z Zilic 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 22 | 2010 |
| A fault tolerant hierarchical network on chip router architecture MH Neishaburi, Z Zilic Journal of Electronic Testing 29, 485-497, 2013 | 21 | 2013 |
| Distributing congestions in nocs through a dynamic routing algorithm based on input and output selections M Daneshtalab, A Pedram, MH Neishaburi, M Riazati, A Afzali-Kusha, ... 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 17 | 2007 |
| NISHA: A fault-tolerant NoC router enabling deadlock-free interconnection of subnets in hierarchical architectures MH Neishaburi, Z Zilic Journal of Systems Architecture 59 (7), 551-569, 2013 | 15 | 2013 |
| Hierarchical embedded logic analyzer for accurate root-cause analysis MH Neishaburi, Z Zilic 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 14 | 2011 |
| HW/SW architecture for soft-error cancellation in real-time operating system K MR, M Daneshtalab, S Safari IEICE Electronics Express 4 (23), 755-761, 2007 | 13 | 2007 |
| Improving robustness of Real-Time Operating Systems (RTOS) services related to soft-errors MH Neishaburi, M Daneshtalab, MR Kakoee, S Safari 2007 IEEE/ACS International Conference on Computer Systems and Applications …, 2007 | 12 | 2007 |
| Dynamic routing algorithm for avoiding hot spots in on-chip networks A Sobhani, M Daneshtalab, MH Neishaburi, MD Mottaghi, A Afzali-Kusha, ... International Conference on Design and Test of Integrated Systems in …, 2006 | 12 | 2006 |
| An infrastructure for debug using clusters of assertion-checkers MH Neishaburi, Z Zilic Microelectronics Reliability 52 (11), 2781-2798, 2012 | 11 | 2012 |
| On a new mechanism of trigger generation for post-silicon debugging MH Neishaburi, Z Zilic IEEE Transactions on Computers 63 (9), 2330-2342, 2013 | 10 | 2013 |
| Debug aware AXI-based network interface MH Neishaburi, Z Zilic 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2011 | 10 | 2011 |
| A distributed AXI-based platform for post-silicon validation MH Neishaburi, Z Zilic 29th VLSI Test Symposium, 8-13, 2011 | 9 | 2011 |
| Hierarchical trigger generation for post-silicon debugging MH Neishaburi, Z Zilic Proceedings of 2011 International Symposium on VLSI Design, Automation and …, 2011 | 9 | 2011 |
| An enhanced debug-aware network interface for Network-on-Chip MH Neishaburi, Z Zilic Thirteenth International Symposium on Quality Electronic Design (ISQED), 709-716, 2012 | 7 | 2012 |
| A UML based system level failure rate assessment technique for SoC designs M Hosseinabady, MH Neishaburi, P Lotfi-Kamran, Z Navabi 25th IEEE VLSI Test Symposium (VTS'07), 243-248, 2007 | 7 | 2007 |
| A hw/sw architecture to reduce the effects of soft-errors in real-time operating system services MH Neishaburi, MR Kakoee, M Daneshtalab, S Safari, Z Navabi 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 1-4, 2007 | 7 | 2007 |
| Using assertions for wireless system monitoring and debugging VN Kallankara, MH Neishaburi, K Radecka, Z Zilic Proceedings of the 8th IEEE International NEWCAS Conference 2010, 401-404, 2010 | 5 | 2010 |
Zeljko ZilicProfessor of Electrical and Computer EngineeringZweryfikowany adres z mcgill.ca
