Farhad Merchant
Farhad Merchant
Lecturer (Assistant Professor), Newcastle University
Zweryfikowany adres z newcastle.ac.uk - Strona główna
Cytowane przez
Cytowane przez
Parameterized posit arithmetic hardware generator
R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018
Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach
D Sisejkovic, F Merchant, LM Reimann, H Srivastava, A Hallawa, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-26, 2021
Deceptive logic locking for hardware integrity protection against machine learning attacks
D Sisejkovic, F Merchant, LM Reimann, R Leupers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
A survey of neuromorphic computing-in-memory: Architectures, simulators, and security
F Staudigl, F Merchant, R Leupers
IEEE Design & Test 39 (2), 90-99, 2021
Next generation arithmetic for edge computing
A Guntoro, C De La Parra, F Merchant, F De Dinechin, JL Gustafson, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism
NN Sharma, R Jain, MM Pokkuluri, SB Patkar, R Leupers, RS Nikhil, ...
Journal of Systems Architecture 135, 102801, 2023
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems
S Nambi, S Ullah, SS Sahoo, A Lohana, F Merchant, A Kumar
IEEE Access 9, 103691-103708, 2021
Control-lock: Securing processor cores against software-controlled hardware trojans
D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 27-32, 2019
Logic locking at the frontiers of machine learning: A survey on developments and opportunities
D Sisejkovic, LM Reimann, E Moussavi, F Merchant, R Leupers
2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ...
Journal of Systems Architecture 60 (7), 592-614, 2014
Efficient and scalable cgra-based implementation of column-wise givens rotation
ZE Rákossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay
2014 IEEE 25th International Conference on Application-Specific Systems …, 2014
NeuroHammer: Inducing bit-flips in memristive crossbar memories
F Staudigl, H Al Indari, D Schön, D Sisejkovic, F Merchant, JM Joseph, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
Qflow: Quantitative information flow for security-aware hardware design in verilog
LM Reimann, L Hanel, D Sisejkovic, F Merchant, R Leupers
2021 IEEE 39th International Conference on Computer Design (ICCD), 603-607, 2021
Efficient realization of householder transform through algorithm-architecture co-design for acceleration of QR factorization
F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan
IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018
Accelerating deep learning inference in constrained embedded devices using hardware loops and a dot product unit
J Vreča, KJX Sturm, E Gungl, F Merchant, P Bientinesi, R Leupers, ...
IEEE Access 8, 165913-165926, 2020
A secure hardware-software solution based on RISC-V, logic locking and microkernel
D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ...
Proceedings of the 23th International Workshop on Software and Compilers for …, 2020
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays
D Bhattacharjee, F Merchant, A Chattopadhyay
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
A fully pipelined modular multiple precision floating point multiplier with vector support
A Baluni, F Merchant, SK Nandy, S Balakrishnan
2011 International Symposium on Electronic System Design, 45-50, 2011
Inter-lock: Logic encryption for processor cores beyond module boundaries
D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss
2019 IEEE European Test Symposium (ETS), 1-6, 2019
Efficient QR decomposition using low complexity column-wise givens rotation (CGR)
F Merchant, A Chattopadhyay, G Garga, SK Nandy, R Narayan, ...
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
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