Farhad Merchant

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Rainer LeupersRWTH AachenZweryfikowany adres z ice.rwth-aachen.de
Anupam ChattopadhyayAssociate Professor, CCDS, NTU, SingaporeZweryfikowany adres z ntu.edu.sg
Lennart M. ReimannRWTH Aachen UniversityZweryfikowany adres z ice.rwth-aachen.de
Sachin PatkarProfessor, Dept. EE, IIT BombayZweryfikowany adres z ee.iitb.ac.in
Simranjeet SinghPh.D. Student, Electrical Engineering, Indian Institute of technology, BombayZweryfikowany adres z ee.iitb.ac.in
Soumyendu RahaProfessor, Computational and Data Sciences, Indian Institute of Science, BengaluruZweryfikowany adres z cds.iisc.ac.in
John GustafsonArizona State UniversityZweryfikowany adres z asu.edu
Elmira MoussaviPhD Student, RWTH Aachen UniversityZweryfikowany adres z ice.rwth-aachen.de
Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyZweryfikowany adres z uni-bremen.de
Tarun VatwaniMicrosoftZweryfikowany adres z microsoft.com
Jonathan NeudorferGroup Manager, Bosch eBike Systems, ReutlingenZweryfikowany adres z de.bosch.com
Akash KumarFull Professor, Chair of Embedded Systems, Ruhr University BochumZweryfikowany adres z rub.de
Chandan Kumar Jha (चंदन कुमार झ...Postdoctoral Researcher at the University of BremenZweryfikowany adres z uni-bremen.de
Ankit BendePhD Researcher, RWTH University | Forschungszentrum JuelichZweryfikowany adres z fz-juelich.de
FURQAN ZAHOORKing Fahd University of Petroleum and Minerals, Saudi ArabiaZweryfikowany adres z kfupm.edu.sa
Felix StaudiglRWTH Aachen UniversityZweryfikowany adres z ice.rwth-aachen.de
Vivek PachauriResearch Group Leader, Interfaces of Bio-NanoSystems, IWE1, RWTH Aachen UniversityZweryfikowany adres z iwe1.rwth-aachen.de
Niraj Nayan SharmaDepartment of Electrical Engineering, IIT BombayZweryfikowany adres z iitb.ac.in
Rohit ChaurasiyaIndian Institute of Technology JammuZweryfikowany adres z iitjammu.ac.in
Rahul ShresthaAssociate Professor, IIT MandiZweryfikowany adres z iitmandi.ac.in

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Farhad Merchant

Assistant Professor, Bernoulli Institute and CogniGron, University of Groningen, The Netherlands

Zweryfikowany adres z rug.nl - Strona główna

Hardware Security Neuromorphic Computing Algorithm-Architecture Co-design Emerging Technologies


Tytuł Sortuj wg cytatów Sortuj wg roku Sortuj wg tytułu	Cytowane przez Cytowane przez	Rok
Parameterized posit arithmetic hardware generator R Chaurasiya, J Gustafson, R Shrestha, J Neudorfer, S Nambiar, K Niyogi, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 334-341, 2018	122	2018
Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach D Sisejkovic, F Merchant, LM Reimann, H Srivastava, A Hallawa, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-26, 2021	68	2021
A survey of neuromorphic computing-in-memory: Architectures, simulators, and security F Staudigl, F Merchant, R Leupers IEEE Design & Test 39 (2), 90-99, 2021	45	2021
Deceptive logic locking for hardware integrity protection against machine learning attacks D Sisejkovic, F Merchant, LM Reimann, R Leupers IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021	43	2021
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism NN Sharma, R Jain, MM Pokkuluri, SB Patkar, R Leupers, RS Nikhil, ... Journal of Systems Architecture 135, 102801, 2023	33*	2023
Next generation arithmetic for edge computing A Guntoro, C De La Parra, F Merchant, F De Dinechin, JL Gustafson, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020	33	2020
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems S Nambi, S Ullah, SS Sahoo, A Lohana, F Merchant, A Kumar IEEE Access 9, 103691-103708, 2021	26	2021
Control-lock: Securing processor cores against software-controlled hardware trojans D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss Proceedings of the 2019 on Great Lakes Symposium on VLSI, 27-32, 2019	25	2019
Logic locking at the frontiers of machine learning: A survey on developments and opportunities D Sisejkovic, LM Reimann, E Moussavi, F Merchant, R Leupers 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021	23	2021
NeuroHammer: Inducing bit-flips in memristive crossbar memories F Staudigl, H Al Indari, D Schön, D Sisejkovic, F Merchant, JM Joseph, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022	21	2022
Qflow: Quantitative information flow for security-aware hardware design in verilog LM Reimann, L Hanel, D Sisejkovic, F Merchant, R Leupers 2021 IEEE 39th International Conference on Computer Design (ICCD), 603-607, 2021	21	2021
Efficient realization of householder transform through algorithm-architecture co-design for acceleration of QR factorization F Merchant, T Vatwani, A Chattopadhyay, S Raha, SK Nandy, R Narayan IEEE Transactions on Parallel and Distributed Systems 29 (8), 1707-1720, 2018	21	2018
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ... Journal of Systems Architecture 60 (7), 592-614, 2014	21	2014
Efficient and scalable cgra-based implementation of column-wise givens rotation ZE Rákossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay 2014 IEEE 25th International Conference on Application-Specific Systems …, 2014	21	2014
A secure hardware-software solution based on RISC-V, logic locking and microkernel D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ... Proceedings of the 23th International Workshop on Software and Compilers for …, 2020	20	2020
Accelerating deep learning inference in constrained embedded devices using hardware loops and a dot product unit J Vreča, KJX Sturm, E Gungl, F Merchant, P Bientinesi, R Leupers, ... IEEE Access 8, 165913-165926, 2020	18	2020
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays D Bhattacharjee, F Merchant, A Chattopadhyay 2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016	18	2016
A fully pipelined modular multiple precision floating point multiplier with vector support A Baluni, F Merchant, SK Nandy, S Balakrishnan 2011 International Symposium on Electronic System Design, 45-50, 2011	18	2011
Inter-Lock: logic encryption for processor cores beyond module boundaries D Šišejković, F Merchant, R Leupers, G Ascheid, S Kegreiss 2019 IEEE European Test Symposium (ETS), 1-6, 2019	17	2019
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation ZE Rákossy, F Merchant, A Acosta-Aponte, SK Nandy, A Chattopadhyay 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014	17	2014

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