Obserwuj
Fengbin Tu
Fengbin Tu
Adjunct Assistant Professor at HKUST
Zweryfikowany adres z ust.hk - Strona główna
Tytuł
Cytowane przez
Cytowane przez
Rok
Deep convolutional neural network architecture with reconfigurable computation patterns
F Tu, S Yin, P Ouyang, S Tang, L Liu, S Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017
2272017
A high energy efficient reconfigurable hybrid neural network processor for deep learning applications
S Yin, P Ouyang, S Tang, F Tu, X Li, S Zheng, T Lu, J Gu, L Liu, S Wei
IEEE Journal of Solid-State Circuits 53 (4), 968-982, 2017
1612017
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications
S Yin, P Ouyang, S Tang, F Tu, X Li, L Liu, S Wei
2017 Symposium on VLSI Circuits, C26-C27, 2017
792017
RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM
F Tu, W Wu, S Yin, L Liu, S Wei
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
652018
A high throughput acceleration for hybrid neural networks with efficient resource management on FPGA
S Yin, S Tang, X Lin, P Ouyang, F Tu, L Liu, S Wei
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
372018
Evolver: A deep learning processor with on-device quantization–voltage–frequency tuning
F Tu, W Wu, Y Wang, H Chen, F Xiong, M Shi, N Li, J Deng, T Chen, L Liu, ...
IEEE Journal of Solid-State Circuits 56 (2), 658-673, 2020
342020
GNA: Reconfigurable and efficient architecture for generative network acceleration
J Yan, S Yin, F Tu, L Liu, S Wei
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
332018
AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs
S Tang, S Yin, S Zheng, P Ouyang, F Tu, L Yao, JZ Wu, W Cheng, L Liu, ...
2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA …, 2017
282017
LCP: A layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA
X Lin, S Yin, F Tu, L Liu, X Li, S Wei
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
262018
Duet: Boosting deep neural network efficiency on dual-module architecture
L Liu, Z Qu, L Deng, F Tu, S Li, X Hu, Z Gu, Y Ding, Y Xie
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
182020
H2learn: High-efficiency learning accelerator for high-accuracy spiking neural networks
L Liang, Z Qu, Z Chen, F Tu, Y Wu, L Deng, G Li, P Li, Y Xie
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
122021
Bit-width adaptive accelerator design for convolution neural network
J Guo, S Yin, P Ouyang, F Tu, S Tang, L Liu, S Wei
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
92018
Rna: A reconfigurable architecture for hardware neural acceleration
F Tu, S Yin, P Ouyang, L Liu, S Wei
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 694-700, 2015
82015
STC: Significance-aware transform-based codec framework for external memory access reduction
F Xiong, F Tu, M Shi, Y Wang, L Liu, S Wei, S Yin
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
72020
Parana: A parallel neural architecture considering thermal problem of 3d stacked memory
S Yin, S Tang, X Lin, P Ouyang, F Tu, J Zhao, C Xu, S Li, Y Xie, SJ Wei
IEEE Transactions on Parallel and Distributed Systems 30 (1), 146-160, 2018
72018
Reconfigurable architecture for neural approximation in multimedia computing
F Tu, S Yin, P Ouyang, L Liu, S Wei
IEEE Transactions on Circuits and Systems for Video Technology 29 (3), 892-906, 2018
72018
Neural approximating architecture targeting multiple application domains
F Tu, S Yin, P Ouyang, L Liu, S Wei
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2509-2512, 2015
62015
DOTA: detect and omit weak attentions for scalable transformer acceleration
Z Qu, L Liu, F Tu, Z Chen, Y Ding, Y Xie
Proceedings of the 27th ACM International Conference on Architectural …, 2022
52022
Neural Networks on Silicon
F Tu
Accessed: Nov, 2019
42019
A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep …
F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 254-256, 2022
32022
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