| Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC ST Zhou, S Katariya, H Ghasemi, S Draper, NS Kim 2010 IEEE International Conference on Computer Design, 112-117, 2010 | 56 | 2010 |
| Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors HR Ghasemi, SC Draper, NS Kim 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 51 | 2011 |
| Low-cost per-core voltage domain support for power-constrained high-performance processors AA Sinkar, HR Ghasemi, MJ Schulte, UR Karpuzcu, NS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 747-758, 2013 | 39 | 2013 |
| Cost-effective power delivery to support per-core voltage domains for power-constrained processors HR Ghasemi, AA Sinkar, MJ Schulte, NS Kim DAC Design Automation Conference 2012, 56-61, 2012 | 36 | 2012 |
| Analyzing the impact of joint optimization of cell size, redundancy, and ECC on low-voltage SRAM array total area NS Kim, SC Draper, ST Zhou, S Katariya, HR Ghasemi, T Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011 | 21 | 2011 |
| RCS: Runtime resource and core scaling for power-constrained multi-core processors HR Ghasemi, NS Kim 2014 23rd International Conference on Parallel Architecture and Compilation …, 2014 | 20 | 2014 |
| An effective VHDL-AMS simulation algorithm with event HR Ghasemi, Z Navabi 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 14 | 2005 |
| Augmenting general purpose processors for network processing HR Ghasemi, H Mohammadi, B Robatmili, N Yazdani Proceedings. 2003 IEEE International Conference on Field-Programmable …, 2003 | 7 | 2003 |
| Workload-adaptive process tuning strategy for power-efficient multi-core processors J Lee, CC Wang, H Ghasemi, L Bircher, Y Cao, NS Kim 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design …, 2010 | 6 | 2010 |
| VR-scale: Runtime dynamic phase scaling of processor voltage regulators for improving power efficiency H Asghari-Moghaddam, HR Ghasemi, AA Sinkar, I Paul, NS Kim Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
| A new synchronization algorithm for (VHDL-AMS) mixed signal simulation HR Ghasemi, Z Navabi IEEE International Symposium on Communications and Information Technology …, 2004 | 5 | 2004 |
| Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications HR Ghasemi, UR Karpuzcu, NS Kim 2015 33rd IEEE International Conference on Computer Design (ICCD), 304-310, 2015 | 4 | 2015 |
| IMPROVING MEMORY RELIABILITY, POWER AND PERFORMANCE USING MIXED-CELL DESIGNS. AR Alameldeen, NS Kim, SM Khan, HR Ghasemi, C Wilkerson, J Kulkarni, ... Intel Technology Journal 17 (1), 2013 | 2 | 2013 |
| UT mixed-signal simulator H Ghasemi, A Gharehbaghi, A Kamran, S Abolmaali, Z Navabi Design Automation and Test in Europe (DATE 2007), 2007 | 1 | 2007 |
| Muli-Issue Multi-Threaded Stream Processor S Sardashti, HR Ghasemi, O Fatemi 2006 IEEE International Conference on Multimedia and Expo, 2041-2044, 2006 | 1 | 2006 |
| A synchronization algorithm for VHDL-AMS simulation with ADA feedback effect HR Ghasemi, Z Navabi Proceedings of the 2004 IEEE International Behavioral Modeling and …, 2004 | 1 | 2004 |
| Line speed IP lookup in software using improved functional units H Mohammadi, B Robatmili, HR Ghasemi, N Yazdani, M Nourani 9th CSICC 2004, 2004 | 1 | 2004 |
| Architecture and Circuit Cross-Cutting Approaches for Power-Efficient Multi-Core Processors HR Ghasemi The University of Wisconsin-Madison, 2015 | | 2015 |
| High Performance Mathematical Quarter-Pixel Motion Estimation with Novel Rate Distortion Metric for H. 264/AVC S Sardashti, HR Ghasemi, M Semsarzadeh, MR Hashemi Computer Society of Iran Computer Conference, 219-226, 2008 | | 2008 |
| MVSP: multithreaded VLIW stream processor S Sardashti, HR Ghasemi, O Fatemi Multimedia on Mobile Devices II 6074, 113-121, 2006 | | 2006 |
