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Florian Zaruba
Florian Zaruba
Axelera AI, ETH Zurich
Verified email at zaruba.email - Homepage
Title
Cited by
Cited by
Year
The Cost of Application-class Processing: Energy and Performance Analysis of a Linux-ready 1.7-GHz 64-bit RISC-V core in 22-nm FDSOI technology
F Zaruba, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (11 …, 2019
1572019
PULPino: A small single-core RISC-V SoC
A Traber, F Zaruba, S Stucki, A Pullini, G Haugou, E Flamand, ...
3rd RISCV Workshop, 2016
642016
Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm FD-SOI
M Cavalcante, F Schuiki, F Zaruba, M Schaffner, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (2), 530-543, 2019
462019
Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
F Zaruba, F Schuiki, T Hoefler, L Benini
IEEE Transactions on Computers, 2020
28*2020
FPnew: An open-source multiformat floating-point unit architecture for energy-proportional transprecision computing
S Mach, F Schuiki, F Zaruba, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 774-787, 2020
272020
OpenPiton+ Ariane: The first open-source, SMP Linux-booting RISC-V system scaling from one to many cores
J Balkind, K Lim, F Gao, J Tu, D Wentzlaff, M Schaffner, F Zaruba, L Benini
Workshop on Computer Architecture Research with RISC-V (CARRV), 1-6, 2019
262019
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
F Zaruba, F Schuiki, L Benini
IEEE Micro, 2020
252020
BYOC: a" bring your own core" framework for heterogeneous-ISA research
J Balkind, K Lim, M Schaffner, F Gao, G Chirkov, A Li, A Lavrov, ...
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
252020
An open-source platform for high-performance non-coherent on-chip communication
A Kurth, W Rönninger, T Benz, M Cavalcante, F Schuiki, F Zaruba, ...
IEEE Transactions on Computers 71 (8), 1794-1809, 2021
182021
Stream semantic registers: A lightweight RISC-V ISA extension achieving full compute utilization in single-issue cores
F Schuiki, F Zaruba, T Hoefler, L Benini
IEEE Transactions on Computers 70 (2), 212-227, 2020
172020
A 0.80 pJ/flop, 1.24 Tflop/sW 8-to-64 bit transprecision floating-point unit for a 64 bit RISC-V processor in 22nm FD-SOI
S Mach, F Schuiki, F Zaruba, L Benini
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019
122019
An open-source verification framework for open-source cores: A RISC-V case study
PD Schiavone, E Sanchez, A Ruospo, F Minervini, F Zaruba, G Haugou, ...
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
112018
The floating point trinity: A multi-modal approach to extreme energy-efficiency and performance
F Zaruba, F Schuiki, S Mach, L Benini
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
92019
Ariane: An open-source 64-bit RISC-V application class processor and latest improvements
F Zaruba, L Benini
Technical talk at the RISC-V Workshop https://www. youtube. com/watch 8, 2018
72018
Pulpino: A risc-v based single-core system
A Traber, S Stucki, F Zaruba, M Gautschi, A Pullini, L Benini
OpenRISC Conference, ORCONF2015, 2015
72015
Indirection stream semantic register architecture for efficient sparse-dense linear algebra
P Scheffler, F Zaruba, F Schuiki, T Hoefler, L Benini
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
62021
ATUNs: Modular and scalable support for atomic operations in a shared memory multiprocessor
A Kurth, S Riedel, F Zaruba, T Hoefler, L Benini
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
42020
Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores
L Bertaccini, M Perotti, S Mach, PD Schiavone, F Zaruba, L Benini
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
32021
Live demonstration: Exploiting body-biasing for static corner trimming and maximum energy efficiency operation in 22nm FDX technology
A Di Mauro, F Zaruba, F Schuiki, S Mach, L Benini
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2020
32020
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
F Zaruba, F Schuiki, L Benini
2020 IEEE Hot Chips 32 Symposium (HCS), 1-24, 2020
32020
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