| Rosetta: A realistic high-level synthesis benchmark suite for software programmable fpgas Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ... Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 82 | 2018 |
| HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing YH Lai, Y Chi, Y Hu, J Wang, CH Yu, Y Zhou, J Cong, Z Zhang Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 73* | 2019 |
| Susy: A programming model for productive construction of high-performance systolic arrays on fpgas YH Lai, H Rong, S Zheng, W Zhang, X Cui, Y Jia, J Wang, B Sullivan, ... 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2020 | 21 | 2020 |
| SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis CH Shih, YH Lai, JHR Jiang 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 442-449, 2015 | 13 | 2015 |
| Synthesis of PCHB-WCHB hybrid quasi-delay insensitive circuits CC Chuang, YH Lai, JHR Jiang Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 11 | 2014 |
| Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits NZ Lee, HY Kuo, YH Lai, JHR Jiang 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 10 | 2016 |
| Programming and synthesis for software-defined FPGA acceleration: status and future prospects YH Lai, E Ustun, S Xiang, Z Fang, H Rong, Z Zhang ACM Transactions on Reconfigurable Technology and Systems (TRETS) 14 (4), 1-39, 2021 | 9 | 2021 |
| A general framework for efficient performance analysis of acyclic asynchronous pipelines YH Lai, CC Chuang, JHR Jiang 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 736-743, 2015 | 7 | 2015 |
| Logic circuit and system and computer program product for logic synthesis C Chuang, YH Lai, J Chiang US Patent 9,576,094, 2017 | 5 | 2017 |
| Scalable synthesis of PCHB–WCHB hybrid quasi-delay insensitive circuits YH Lai, CC Chuang, JHR Jiang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 4 | 2016 |
| Bring your own codegen to deep learning compiler Z Chen, CH Yu, T Morris, J Tuyls, YH Lai, J Roesch, E Delaye, V Sharma, ... arXiv preprint arXiv:2105.03215, 2021 | 3 | 2021 |
| HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs S Xiang, YH Lai, Y Zhou, H Chen, N Zhang, D Pal, Z Zhang Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 2 | 2022 |
| Network logic synthesis C Chuang, YH Lai, J Chiang US Patent 10,496,773, 2019 | 1 | 2019 |
| Computer product for making a semiconductor device C Chuang, YH Lai, J Chiang US Patent 11,120,183, 2021 | | 2021 |
| Asynchronous pipeline circuit YH Lai, CH Shih, J Chiang US Patent 10,157,249, 2018 | | 2018 |
| Asynchronous QDI circuit synthesis from signal transition protocols BY Huang, YH Lai, JHR Jiang 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 434-441, 2015 | | 2015 |
| 無環非同步類延遲非敏感電路之統一建模與高效效能分析 賴奕翔 國立臺灣大學, 2015 | | 2015 |
