Obserwuj
Mikael Millberg
Mikael Millberg
Zweryfikowany adres z kth.se
Tytuł
Cytowane przez
Cytowane przez
Rok
A network on chip architecture and design methodology
S Kumar, A Jantsch, JP Soininen, M Forsell, M Millberg, J Oberg, ...
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms …, 2002
17722002
Network on chip: An architecture for billion transistor era
A Hemani, A Jantsch, S Kumar, A Postula, J Oberg, M Millberg, ...
Proceeding of the IEEE NorChip Conference 31 (20), 0, 2000
6322000
Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
M Millberg, E Nilsson, R Thid, A Jantsch
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
5232004
The Nostrum backbone-a communication protocol stack for networks on chip
M Millberg, E Nilsson, R Thid, S Kumar, A Jantsch
17th International Conference on VLSI Design. Proceedings., 693-696, 2004
3102004
Load distribution with the proximity congestion awareness in a network on chip
E Nilsson, M Millberg, J Oberg, A Jantsch
2003 Design, Automation and Test in Europe Conference and Exhibition, 1126-1127, 2003
2272003
NNSE: Nostrum network-on-chip simulation environment
Z Lu, R Thid, M Millberg, E Nilsson, A Jantsch
Swedish system-on-chip conference, 2005
1052005
FPGA resource and timing estimation from Matlab execution traces
P Bjuréus, M Millberg, A Jantsch
Proceedings of the Tenth International Symposium on Hardware/Software …, 2002
682002
Flow regulation for on-chip communication
Z Lu, M Millberg, A Jantsch, A Bruce, P van der Wolf, T Henriksson
2009 Design, Automation & Test in Europe Conference & Exhibition, 578-581, 2009
452009
Evaluating NoC communication backbones with simulation
R Thid, M Millberg, A Jantsch
The IEEE NorChip Conference, Riga, Latvia, Nov 10-11, 2003, 27-30, 2003
442003
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures.
D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen
VLSI-SOC, 362-, 2003
322003
Implementation of a pulse coupled neural network in FPGA
J Waldemark, M Millberg, T Lindblad, K Waldemark, V Becanovic
International Journal of Neural Systems 10 (03), 171-177, 2000
232000
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
D Pamunuwa, J Öberg, LR Zheng, M Millberg, A Jantsch, H Tenhunen
Integration 38 (1), 3-17, 2004
202004
Image analysis for airborne reconnaissance and missile applications
J Waldemark, M Millberg, T Lindblad, K Waldemark
Pattern Recognition Letters 21 (3), 239-251, 2000
122000
Generic VHDL implementation of a PCNN with loadable coefficients
M Millberg, J Oberg, JTA Waldemark
Ninth Workshop on Virtual Intelligence/Dynamic Neural Networks 3728, 186-197, 1999
101999
Pulse-coupled neural network implementation in FPGA
JTA Waldemark, T Lindblad, CS Lindsey, KE Waldemark, J Oberg, ...
Applications and Science of Computational Intelligence 3390, 392-402, 1998
81998
Johny berg, Kari Tiensyrja, and Ahmed Hemani. A network on chip architecture and design methodology
S Kumar, A Jantsch, JP Soininen, M Forsell, M Millberg
ISVLSI 2, 117, 0
7
Priority based forced requeue to reduce worst-case latencies for bursty traffic
M Millberg, A Jantsch
2009 Design, Automation & Test in Europe Conference & Exhibition, 1070-1075, 2009
52009
Increasing NoC performance and utilisation using a dual packet exit strategy
M Millberg, A Jantsch
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
42007
An efficient dynamic memory manager for embedded systems
M Millberg, A Postula, A Hemani
Proceedings of the ICDA Conference, 2000
42000
Architectural techniques for improving performance in networks on chip
M Millberg
KTH Royal Institute of Technology, 2011
32011
Nie można teraz wykonać tej operacji. Spróbuj ponownie później.
Prace 1–20