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Muhammad Khellah
Muhammad Khellah
Zweryfikowany adres z intel.com
Tytuł
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Trading off cache capacity for reliability to enable low voltage operation
C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu
ACM SIGARCH computer architecture news 36 (3), 203-214, 2008
3532008
A 45 nm resilient microprocessor core for dynamic variation tolerance
KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ...
IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010
3152010
Floating-body dynamic random access memory and method of fabrication in tri-gate technology
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,098,507, 2006
2422006
Floating-body memory cell write
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,061,806, 2006
1322006
Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs
M Khellah, Y Ye, N Kim, D Somasekhar, G Pandya, A Farhang, K Zhang, ...
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 9-10, 2006
1302006
Floating-body DRAM using write word line for increased retention time
S Tang, A Keshavarzi, D Somasekhar, F Paillet, M Khellah, Y Ye, V De
US Patent 6,903,984, 2005
1222005
Multi-phase 1 GHz voltage doubler charge pump in 32 nm logic process
D Somasekhar, B Srinivasan, G Pandya, F Hamzaoglu, M Khellah, ...
IEEE Journal of Solid-State Circuits 45 (4), 751-758, 2010
1182010
Purge-based floating body memory
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,230,846, 2007
1122007
OTP antifuse cell and cell array
F Paillet, A Keshavarzi, MM Khellah, D Somasekhar, Y Ye, SH Tang, ...
US Patent 7,102,951, 2006
1122006
Floating-body dynamic random access memory with purge line
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,002,842, 2006
1122006
Method and apparatus to generate a reference value in a memory array
D Somasekhar, Y Ye, MM Khellah, F Paillet, SH Tang, A Keshavarzi, ...
US Patent 6,952,376, 2005
1112005
Method for making memory cell without halo implant
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,001,811, 2006
1102006
Asymmetric memory cell
A Keshavarzi, SH Tang, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 6,992,339, 2006
1102006
Floating-body DRAM with two-phase write
SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ...
US Patent 7,072,205, 2006
1062006
A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS
R Jain, BM Geuskens, ST Kim, MM Khellah, J Kulkarni, JW Tschanz, V De
IEEE Journal of Solid-State Circuits 49 (4), 917-927, 2014
1042014
SRAM array with dynamic voltage for reducing active leakage power
M Khellah, V De, D Somasekhar, Y Ye
US Patent 6,724,648, 2004
912004
2 GHz 2 Mb 2T gain cell memory macro with 128 GBytes/sec bandwidth in a 65 nm logic process technology
D Somasekhar, Y Ye, P Aseron, SL Lu, MM Khellah, J Howard, G Ruhl, ...
IEEE Journal of Solid-State Circuits 44 (1), 174-185, 2008
902008
Accurate estimation of SRAM dynamic stability
DE Khalil, M Khellah, NS Kim, Y Ismail, T Karnik, VK De
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (12 …, 2008
872008
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
A Raychowdhury, B Geuskens, J Kulkarni, J Tschanz, K Bowman, ...
2010 IEEE International Solid-State Circuits Conference-(ISSCC), 352-353, 2010
802010
Serial-link bus: A low-power on-chip bus architecture
M Ghoneima, Y Ismail, MM Khellah, J Tschanz, V De
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 2020-2032, 2008
792008
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