Naoya Onizawa
Naoya Onizawa
Research Institute of Electrical Communication, Tohoku University
Zweryfikowany adres z tohoku.ac.jp
Tytuł
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VLSI implementation of deep neural network using integral stochastic computing
A Ardakani, F Leduc-Primeau, N Onizawa, T Hanyu, WJ Gross
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
1762017
Standby-power-free integrated circuits using MTJ-based VLSI computing
T Hanyu, T Endoh, D Suzuki, H Koike, Y Ma, N Onizawa, M Natsui, ...
Proceedings of the IEEE 104 (10), 1844-1863, 2016
882016
Gabor filter based on stochastic computation
N Onizawa, D Katagiri, K Matsumiya, WJ Gross, T Hanyu
IEEE Signal Processing Letters 22 (9), 1224-1228, 2015
532015
Design of high-throughput fully parallel LDPC decoders based on wire partitioning
N Onizawa, T Hanyu, VC Gaudet
IEEE transactions on very large scale integration (VLSI) systems 18 (3), 482-489, 2009
532009
Algorithm and architecture for a low-power content-addressable memory based on sparse clustered networks
H Jarollahi, V Gripon, N Onizawa, WJ Gross
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (4), 642-653, 2014
442014
Architecture and implementation of an associative memory using sparse clustered networks
H Jarollahi, N Onizawa, V Gripon, WJ Gross
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2901-2904, 2012
392012
A nonvolatile associative memory-based context-driven search engine using 90 nm CMOS/MTJ-hybrid logic-in-memory architecture
H Jarollahi, N Onizawa, V Gripon, N Sakimura, T Sugibayashi, T Endoh, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4 (4 …, 2014
382014
Asynchronous protocol converter
T Hanyu, N Onizawa
US Patent 9,111,051, 2015
362015
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop
S Oosawa, T Konishi, N Onizawa, T Hanyu
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
352015
High-throughput low-energy content-addressable memory based on self-timed overlapped search mechanism
N Onizawa, S Matsunaga, VC Gaudet, T Hanyu
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012
332012
A low-power content-addressable memory based on clustered-sparse networks
H Jarollahi, V Gripon, N Onizawa, WJ Gross
2013 IEEE 24th International Conference on Application-Specific Systems …, 2013
292013
Reduced-complexity binary-weight-coded associative memories
H Jarollahi, N Onizawa, V Gripon, WJ Gross
2013 IEEE International Conference on Acoustics, Speech and Signal …, 2013
282013
High-throughput compact delay-insensitive asynchronous NoC router
N Onizawa, A Matsumoto, T Funazaki, T Hanyu
IEEE Transactions on Computers 63 (3), 637-649, 2013
282013
Analog-to-stochastic converter using magnetic-tunnel junction devices
N Onizawa, D Katagiri, WJ Gross, T Hanyu
Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014
262014
Low-energy asynchronous interleaver for clockless fully parallel LDPC decoding
N Onizawa, VC Gaudet, T Hanyu
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (8), 1933-1943, 2011
262011
Analog-to-stochastic converter using magnetic tunnel junction devices for vision chips
N Onizawa, D Katagiri, WJ Gross, T Hanyu
IEEE Transactions on Nanotechnology 15 (5), 705-714, 2015
242015
High-throughput low-energy self-timed CAM based on reordered overlapped search mechanism
N Onizawa, S Matsunaga, VC Gaudet, WJ Gross, T Hanyu
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (3), 865-876, 2013
242013
3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm
N Onizawa, T Ikeda, T Hanyu, VC Gaudet
2007 50th Midwest Symposium on Circuits and Systems, 217-220, 2007
232007
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm
T Hanyu, D Suzuki, N Onizawa, S Matsunaga, M Natsui, A Mochizuki
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
222015
Efficient CMOS invertible logic using stochastic computing
SC Smithson, N Onizawa, BH Meyer, WJ Gross, T Hanyu
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2263-2274, 2019
182019
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