| Impact of interface trap charges on the performances of junctionless MOSFET in sub-threshold regime T Ganguli, M Chanda, A Sarkar Computers and Electrical Engineering 100, 107914, 2022 | 8 | 2022 |
| Energy efficient adiabatic logic styles in sub-threshold region for ultra low power application M Chanda, T Ganguli, S Mal, A Podder, CK Sarkar Journal of Low Power Electronics 13 (3), 472-481, 2017 | 7 | 2017 |
| Analysis of double-gate junctionless MOSFET for energy efficient digital application A Mukherjee, D Banerjee, T Ganguli, A Sarkar 2021 Devices for Integrated Circuit (DevIC), 545-549, 2021 | 4 | 2021 |
| Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application M Chanda, J Basak, D Sinha, T Ganguli, CK Sarkar 2016 International Conference on Communication and Signal Processing (ICCSP …, 2016 | 4 | 2016 |
| Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application M Chanda, D Sinha, J Basak, T Ganguli, CK Sarkar 2016 International Conference on Communication and Signal Processing (ICCSP …, 2016 | 2 | 2016 |
| Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application M Chanda, J Basak, D Sinha, T Ganguli, CK Sarkar 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 37-41, 2016 | 1 | 2016 |
| Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit T Ganguli, M Chanda, A Sarkar IEEE Transactions on Electron Devices, 2023 | | 2023 |
| Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application M Chanda, D Sinha, J Basak, T Ganguli, CK Sarkar 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 42-47, 2016 | | 2016 |
