| Proces boloński A Kraśniewski To już 10, 2009 | 257* | 2009 |
| Circular self-test path: A low-cost BIST technique for VLSI circuits A Krasniewski, S Pilarski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989 | 196 | 1989 |
| Jak przygotowywać programy kształcenia zgodnie z wymaganiami Krajowych Ram Kwalifikacji dla Szkolnictwa Wyższego? A Kraśniewski Ministerstwo Nauki i Szkolnictwa Wyższego, 2011 | 84 | 2011 |
| Application-dependent testing of FPGA delay faults A Krasniewski Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for …, 1999 | 61 | 1999 |
| Circular self-test path: A low-cost BIST technique A Krasniewski, S Pilarski 24th ACM/IEEE Design Automation Conference, 407-415, 1987 | 58 | 1987 |
| Automatic design of exhaustively self-testing chips with BILBO modules. A Krasniewski, A Albicki International Test Conference 1985, 1985, 1985 | 58 | 1985 |
| Balanced multilevel decomposition and its applications in FPGA-based synthesis T Łuba, H Selvaraj, M Nowicka, A Kraśniewski Logic and Architecture Synthesis: State-of-the-art and novel approaches, 109-115, 1995 | 54 | 1995 |
| A clock distribution scheme for large RSFQ circuits K Gaj, EG Friedman, MJ Feldman, A Krasniewski IEEE Transactions on Applied Superconductivity 5 (2), 3320-3324, 1995 | 51 | 1995 |
| Estimating testing effectiveness of the circular self-test path technique S Pilarski, A Krasniewski, T Kameda IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 49 | 1992 |
| Design and low speed testing of a four-bit RSFQ multiplier-accumulator QP Herr, N Vukovic, CA Mancini, K Gaj, Q Ke, V Adler, EG Friedman, ... IEEE transactions on applied superconductivity 7 (2), 3168-3171, 1997 | 47 | 1997 |
| Flexibility and adaptability in engineering education: an academic institution perspective A Krasniewski, J Woznicki IEEE Transactions on Education 41 (4), 237-246, 1998 | 38 | 1998 |
| Logic simulation of RSFQ circuits A Krasniewski IEEE transactions on applied superconductivity 3 (1), 33-38, 1993 | 38 | 1993 |
| Exploiting reconfigurability for effective detection of delay faults in LUT-based FPGAs A Krasniewski Field-Programmable Logic and Applications: The Roadmap to Reconfigurable …, 2000 | 24 | 2000 |
| Combining serial decomposition with topological partitioning for effective multi-level pla implementations T Luba, J Kalinowski, K Jasinski, H Krasniewski Proc. IFIP Working Conference on Logic and Architecture Synthesis, 77-86, 1990 | 24 | 1990 |
| Testing FPGA delay faults in the system environment is very different from" ordinary" delay fault testing A Krasniewski Proceedings Seventh International On-Line Testing Workshop, 37-40, 2001 | 21 | 2001 |
| Synthesis of finite state machines for implementation with programmable structures T Łuba, G Borowik, A Kraśniewski Electronics and Telecommunications Quarterly 55 (2), 183-200, 2009 | 20 | 2009 |
| Polska rama kwalifikacji A Chłoń-Domińczak, S Sławiński, A Kraśniewski, E Chmielecka Instytut Badań Edukacyjnych, 2015 | 19 | 2015 |
| Concurrent error detection in sequential circuits implemented using FPGAs with embedded memory blocks A Krasniewski Proceedings. 10th IEEE International On-Line Testing Symposium, 67-72, 2004 | 19 | 2004 |
| Korzyści i koszty związane z przystąpieniem Polski do Unii Europejskiej w sferze szkolnictwa wyższego E Chmielecka, A Kraśniewski, J Woźnicki Wydawnictwo Urzędu komitetu Integracji Europejskiej, 2003 | 19 | 2003 |
| Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs A Krasniewski Microprocessors and Microsystems 32 (5-6), 303-312, 2008 | 18 | 2008 |
