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(Cody) Hao Yu
(Cody) Hao Yu
Senior Applied Scientist at Amazon AI, AWS | PhD of UCLA
Zweryfikowany adres z amazon.com - Strona główna
Tytuł
Cytowane przez
Cytowane przez
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Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs
X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
3352017
Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale
M Huang, D Wu, CH Yu, Z Fang, M Interlandi, T Condie, J Cong
Proceedings of the Seventh ACM Symposium on Cloud Computing, 456-469, 2016
942016
Ansor: Generating {High-Performance} Tensor Programs for Deep Learning
L Zheng, C Jia, M Sun, Z Wu, CH Yu, A Haj-Ali, Y Wang, J Yang, D Zhuo, ...
14th USENIX symposium on operating systems design and implementation (OSDI …, 2020
922020
The SMEM Seeding Acceleration for DNA Sequence Alignment
MCF Chang, YT Chen, J Cong, PT Huang, CL Kuo, CH Yu
The 24th IEEE International Symposium on Field-Programmable Custom Computing …, 2016
552016
TGPA: tile-grained pipeline architecture for low latency CNN inference
X Wei, Y Liang, X Li, CH Yu, P Zhang, J Cong
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
512018
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS
J Cong, P Wei, CH Yu, P Zhou
472017
HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing
YH Lai, Y Chi, Y Hu, J Wang, CH Yu, Y Zhou, J Cong, Z Zhang
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
462019
Automated accelerator generation and optimization with composable, parallel and pipeline architecture
J Cong, P Wei, CH Yu, P Zhang
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
442018
On the preconditioner of conjugate gradient method: a power grid simulation perspective
CH Chou, NY Tsai, H Yu, CR Lee, Y Shi, SC Chang
Proceedings of the International Conference on Computer-Aided Design, 494-497, 2010
362010
Heterogeneous datacenters: Options and opportunities
J Cong, M Huang, D Wu, CH Yu
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
262016
Best-effort FPGA programming: A few steps can go a long way
J Cong, Z Fang, Y Hao, P Wei, CH Yu, C Zhang, P Zhou
arXiv preprint arXiv:1807.01340, 2018
252018
S2FA: An accelerator automation framework for heterogeneous computing in datacenters
CH Yu, P Wei, M Grossman, P Zhang, V Sarker, J Cong
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
252018
Useful-skew clock optimization for multi-power mode designs
HM Chou, H Yu, SC Chang
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 647-650, 2011
212011
Latte: Locality Aware Transformation for High-Level Synthesis
J Cong, P Wei, CH Yu, P Zhou
172018
Thermal-aware on-line scheduler for 3-D many-core processor throughput optimization
CH Yu, CL Lung, YL Ho, RS Hsu, DM Kwai, SC Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
162014
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
A Sohrabizadeh, CH Yu, M Gao, J Cong
ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (4 …, 2022
122022
Analysis and optimization of the implicit broadcasts in FPGA HLS to improve maximum frequency
L Guo, J Lau, Y Chi, J Wang, CH Yu, Z Chen, Z Zhang, J Cong
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
122020
Customizable computing—from single chip to datacenters
J Cong, Z Fang, M Huang, P Wei, D Wu, CH Yu
Proceedings of the IEEE 107 (1), 185-203, 2018
112018
Overcoming data transfer bottlenecks in dnn accelerators via layer-conscious memory managment
X Wei, Y Liang, P Zhang, CH Yu, J Cong
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
82019
From {JVM} to {FPGA}: Bridging Abstraction Hierarchy via Optimized Deep Pipelining
J Cong, P Wei, CH Yu
10th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 18), 2018
72018
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