| Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 335 | 2017 |
| Programming and runtime support to blaze FPGA accelerator deployment at datacenter scale M Huang, D Wu, CH Yu, Z Fang, M Interlandi, T Condie, J Cong Proceedings of the Seventh ACM Symposium on Cloud Computing, 456-469, 2016 | 94 | 2016 |
| Ansor: Generating {High-Performance} Tensor Programs for Deep Learning L Zheng, C Jia, M Sun, Z Wu, CH Yu, A Haj-Ali, Y Wang, J Yang, D Zhuo, ... 14th USENIX symposium on operating systems design and implementation (OSDI …, 2020 | 92 | 2020 |
| The SMEM Seeding Acceleration for DNA Sequence Alignment MCF Chang, YT Chen, J Cong, PT Huang, CL Kuo, CH Yu The 24th IEEE International Symposium on Field-Programmable Custom Computing …, 2016 | 55 | 2016 |
| TGPA: tile-grained pipeline architecture for low latency CNN inference X Wei, Y Liang, X Li, CH Yu, P Zhang, J Cong 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 51 | 2018 |
| Bandwidth Optimization Through On-Chip Memory Restructuring for HLS J Cong, P Wei, CH Yu, P Zhou | 47 | 2017 |
| HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing YH Lai, Y Chi, Y Hu, J Wang, CH Yu, Y Zhou, J Cong, Z Zhang Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 46 | 2019 |
| Automated accelerator generation and optimization with composable, parallel and pipeline architecture J Cong, P Wei, CH Yu, P Zhang 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018 | 44 | 2018 |
| On the preconditioner of conjugate gradient method: a power grid simulation perspective CH Chou, NY Tsai, H Yu, CR Lee, Y Shi, SC Chang Proceedings of the International Conference on Computer-Aided Design, 494-497, 2010 | 36 | 2010 |
| Heterogeneous datacenters: Options and opportunities J Cong, M Huang, D Wu, CH Yu Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 26 | 2016 |
| Best-effort FPGA programming: A few steps can go a long way J Cong, Z Fang, Y Hao, P Wei, CH Yu, C Zhang, P Zhou arXiv preprint arXiv:1807.01340, 2018 | 25 | 2018 |
| S2FA: An accelerator automation framework for heterogeneous computing in datacenters CH Yu, P Wei, M Grossman, P Zhang, V Sarker, J Cong 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018 | 25 | 2018 |
| Useful-skew clock optimization for multi-power mode designs HM Chou, H Yu, SC Chang 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 647-650, 2011 | 21 | 2011 |
| Latte: Locality Aware Transformation for High-Level Synthesis J Cong, P Wei, CH Yu, P Zhou | 17 | 2018 |
| Thermal-aware on-line scheduler for 3-D many-core processor throughput optimization CH Yu, CL Lung, YL Ho, RS Hsu, DM Kwai, SC Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 16 | 2014 |
| AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators A Sohrabizadeh, CH Yu, M Gao, J Cong ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (4 …, 2022 | 12 | 2022 |
| Analysis and optimization of the implicit broadcasts in FPGA HLS to improve maximum frequency L Guo, J Lau, Y Chi, J Wang, CH Yu, Z Chen, Z Zhang, J Cong 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 12 | 2020 |
| Customizable computing—from single chip to datacenters J Cong, Z Fang, M Huang, P Wei, D Wu, CH Yu Proceedings of the IEEE 107 (1), 185-203, 2018 | 11 | 2018 |
| Overcoming data transfer bottlenecks in dnn accelerators via layer-conscious memory managment X Wei, Y Liang, P Zhang, CH Yu, J Cong Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 8 | 2019 |
| From {JVM} to {FPGA}: Bridging Abstraction Hierarchy via Optimized Deep Pipelining J Cong, P Wei, CH Yu 10th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 18), 2018 | 7 | 2018 |
Jingsheng Jason CongVolgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, UniversityZweryfikowany adres z cs.ucla.edu
