Obserwuj
Andrew Waterman
Andrew Waterman
UC Berkeley
Zweryfikowany adres z eecs.berkeley.edu
Tytuł
Cytowane przez
Cytowane przez
Rok
Roofline: an insightful visual performance model for multicore architectures
S Williams, A Waterman, D Patterson
Communications of the ACM 52 (4), 65-76, 2009
31262009
Single-chip microprocessor that communicates directly using light
C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ...
Nature 528 (7583), 534-538, 2015
14022015
Chisel: constructing hardware in a scala embedded language
J Bachrach, H Vo, B Richards, Y Lee, A Waterman, R Avižienis, ...
Proceedings of the 49th Annual Design Automation Conference, 1216-1225, 2012
13072012
The RISC-V instruction set manual, volume I: User-level ISA, version 2.0
A Waterman, Y Lee, DA Patterson, K Asanovic
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2014
1021*2014
The rocket chip generator
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016
8922016
Design of the RISC-V instruction set architecture
AS Waterman
University of California, Berkeley, 2016
2682016
The risc-v instruction set manual, volume i: Base user-level isa
A Waterman, Y Lee, DA Patterson, K Asanovic
EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62 116, 1-32, 2011
2612011
The RISC-V instruction set manual, volume II: Privileged architecture
A Waterman, K Asanovic, J Hauser
RISC-V Foundation, 1-4, 2019
2042019
RAMP gold: an FPGA-based architecture simulator for multiprocessors
Z Tan, A Waterman, R Avizienis, Y Lee, H Cook, D Patterson, K Asanović
Proceedings of the 47th Design Automation Conference, 463-468, 2010
1862010
A 45nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators
Y Lee, A Waterman, R Avizienis, H Cook, C Sun, V Stojanović, K Asanović
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 199-202, 2014
1812014
An agile approach to building RISC-V microprocessors
Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ...
ieee Micro 36 (2), 8-20, 2016
1672016
The rocket chip generator. EECS Department
K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4, 6-2, 2016
1592016
The risc-v instruction set manual volume i: Unprivileged isa
A Waterman, K Asanovic
Document Version 20191213, 1-4, 2019
1572019
The RISC-V instruction set manual volume II: Privileged architecture version 1.7
A Waterman, Y Lee, R Avizienis, DA Patterson, K Asanovic
EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-49, 2015
1552015
The RISC-V Reader: an open architecture Atlas
D Patterson, A Waterman
Strawberry Canyon, 2017
1422017
A case for FAME: FPGA architecture model execution
Z Tan, A Waterman, H Cook, S Bird, K Asanović, D Patterson
Proceedings of the 37th annual international symposium on Computer …, 2010
1182010
A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ...
IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016
872016
The risc-v instruction set manual, volume i: Base user-level isa. EECS Department
A Waterman, Y Lee, DA Patterson, K Asanovic
University of California, 2011
632011
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ...
2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015
552015
Processes and resource management in a scalable many-core OS
K Klues, B Rhoden, Y Zhu, A Waterman, E Brewer
HotPar10, Berkeley, CA, 106-109, 2010
482010
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