ADMM-based infinity-norm detection for massive MIMO: Algorithm and VLSI architecture S Shahabuddin, I Hautala, M Juntti, C Studer IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 747-759, 2021 | 29 | 2021 |
Programmable low-power multicore coprocessor architecture for HEVC/H. 265 in-loop filtering I Hautala, J Boutellier, J Hannuksela, O Silven IEEE Transactions on Circuits and Systems for Video Technology 25 (7), 1217-1230, 2014 | 19 | 2014 |
Programmable lowpower implementation of the HEVC adaptive loop filter I Hautala, J Boutellier, J Hannuksela 2013 IEEE International Conference on Acoustics, Speech and Signal …, 2013 | 11 | 2013 |
Executing dynamic data rate actor networks on OpenCL platforms J Boutellier, I Hautala 2016 IEEE International Workshop on Signal Processing Systems (siPS), 98-103, 2016 | 10 | 2016 |
An embedded programmable processor for compressive sensing applications M Safarpour, I Hautala, O Silvén 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2018 | 7 | 2018 |
Programmable 28nm coprocessor for HEVC/H. 265 in-loop filters I Hautala, J Boutellier, O Silvén Circuits and Systems (ISCAS), 2016 IEEE International Symposium on, 1570-1573, 2016 | 6 | 2016 |
From dataflow models to energy efficient application specific processors I Hautala University of Oulu, 2019 | 5 | 2019 |
Toward efficient execution of RVC-CAL dataflow programs on multicore platforms I Hautala, J Boutellier, T Nyländen, O Silvén Journal of Signal Processing Systems 90, 1507-1517, 2018 | 5 | 2018 |
Programmable data parallel accelerator for mobile computer vision T Nyländen, H Kultala, I Hautala, J Boutellier, J Hannuksela, O Silvén 2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2015 | 4 | 2015 |
Transport triggered array processor for vision applications M Safarpour, I Hautala, M Bordallo López, O Silvén Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th …, 2019 | 2 | 2019 |
TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow I Hautala, J Boutellier, O Silvén IEEE Transactions on Computers 69 (1), 51-64, 2019 | 1 | 2019 |
Transport Triggered Array Processor for Vision Applications: Near-threshold Performance Loss Compensation Through Inherent Parallelism of Vision Array Processors M Safarpour Authorea Preprints, 2023 | | 2023 |
Sovelluskohtainen signaaliprosessori HEVC ALF-suodattimelle I Hautala I. Hautala, 2013 | | 2013 |
SiPS 2017 additionnal reviewers M Deyoung, C Langlais, E Cherny, H Andrade, M Léonardon, J Choi, ... | | |
HEVC ALF-SUODATTIMELLE I Hautala | | |