Ultra low power circuit design using tunnel FETs R Mukundrajan, M Cotter, V Saripalli, MJ Irwin, S Datta, V Narayanan 2012 IEEE Computer Society Annual Symposium on VLSI, 153-158, 2012 | 45 | 2012 |
Design of energy‐efficient circuits and systems using tunnel field effect transistors R Mukundrajan, M Cotter, S Bae, V Saripalli, MJ Irwin, S Datta, ... IET Circuits, Devices & Systems 7 (5), 294-303, 2013 | 14 | 2013 |
Scoc ip cores for custom built supercomputing nodes V Nagarajan, R Hariharan, V Srinivasan, RS Kannan, P Thinakaran, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 255-260, 2012 | 12 | 2012 |
Compilation accelerator on silicon V Nagarajan, V Srinivasan, R Kannan, P Thinakaran, R Hariharan, ... 2012 IEEE Computer Society Annual Symposium on VLSI, 267-272, 2012 | 10 | 2012 |
Towards resilient micro-architectures: Datapath reliability enhancement using STT-MRAM K Swaminathan, R Mukundrajan, N Soundararajan, V Narayanan 2011 IEEE Computer Society Annual Symposium on VLSI, 236-241, 2011 | 10 | 2011 |
Custom built heterogeneous multi-core architectures (cubemach): Breaking the conventions N Venkateswaran, KP Saravanan, NC Nachiappan, A Vasudevan, ... 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 8 | 2010 |
Enabling architectural innovations using non-volatile memory V Narayanan, V Saripalli, K Swaminathan, R Mukundrajan, G Sun, Y Xie, ... Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011 | 7 | 2011 |
Towards Modeling and Design Automation of Supercomputing Clusters: SuperComputer-On-Chip (SCOS) IP Cores R Mukundrajan A Thesis Proposal Submitted to Waran Research Foundation Link: http://www …, 2009 | 4 | 2009 |
Towards modeling and integrated design automation of supercomputing clusters (MIDAS) V Nagarajan, A Vasudevan, B Subramaniam, R Mukundrajan, ... Computer Science-Research and Development 24, 1-10, 2009 | 3 | 2009 |
Tunnel FET based field programmable gate arrays R Mukundrajan | 1 | 2011 |
A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient N Venkateswaran, R Mukundrajan, M Sharma, B Ravi 2009 IEEE Computer Society Annual Symposium on VLSI, 49-54, 2009 | | 2009 |
Conference: Annual Symposium on VLSI 2012, ISVLSI-12 at University of Massachusetts Amherst Title: Compilation Accelerator on Silicon V Nagarajan, V Srinivasan, RS Kannan, P Thinakaran, R Hariharan, ... | | |