Simon Moore

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	Wszystkie	Od 2018
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Robert N. M. WatsonProfessor, Department of Computer Science and Technology, University of CambridgeZweryfikowany adres z cl.cam.ac.uk
Dr. Jonathan WoodruffResearch Associate, Cambridge UniversityZweryfikowany adres z cam.ac.uk
Robert MullinsComputer Laboratory, University of CambridgeZweryfikowany adres z cl.cam.ac.uk
Brooks DavisPrinciple Computer Scientist, SRI InternationalZweryfikowany adres z one-eyed-alien.net
David ChisnallUniversity of CambridgeZweryfikowany adres z swan.ac.uk
Ben LaurieGoogle, University of Cambridge, UCLZweryfikowany adres z google.com
Jonathan AndersonMemorial University of NewfoundlandZweryfikowany adres z mun.ca
Steven J. MurdochDepartment of Computer Science, University College LondonZweryfikowany adres z ucl.ac.uk
Peter RobinsonProfessor of Computer Technology, University of CambridgeZweryfikowany adres z cam.ac.uk
Paul FoxResearch Associate, University of CambridgeZweryfikowany adres z cl.cam.ac.uk
Ross AndersonUniversity of CambridgeZweryfikowany adres z cl.cam.ac.uk
Christian FenschARM NorwayZweryfikowany adres z arm.com
Danielle (Dani) S. BassettJ. Peter Skirkanich Professor, University of Pennsylvania & Santa Fe InstituteZweryfikowany adres z seas.upenn.edu
Andrew W. MooreUniversity of CambridgeZweryfikowany adres z cl.cam.ac.uk
G.J.M. Smithoogleraar CAES Universiteit TwenteZweryfikowany adres z utwente.nl
Jeong-Gun LeeProfessor of Computer Engineering, Hallym UniversityZweryfikowany adres z hallym.ac.kr
Dr Simon J. HollisResearch Scientist at Facebook Reality LabsZweryfikowany adres z fb.com
Philip M. WattsDepartment of Electronic and Electrical Engineering, University College LondonZweryfikowany adres z ucl.ac.uk
Steve FurberProfessor of Computer Engineering, Department of Computer Science, The University of Manchester, UKZweryfikowany adres z manchester.ac.uk

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Simon Moore

Professor of Computer Engineering, University of Cambridge

Zweryfikowany adres z cl.cam.ac.uk - Strona główna

Computer Architecture Security VLSI Design System Photonics


Tytuł Sortuj wg cytatów Sortuj wg roku Sortuj wg tytułu	Cytowane przez Cytowane przez	Rok
Low-latency virtual-channel routers for on-chip networks R Mullins, A West, S Moore ACM SIGARCH Computer Architecture News 32 (2), 188, 2004	660	2004
Efficient physical embedding of topologically complex information processing networks in brains and computer circuits DS Bassett, DL Greenfield, A Meyer-Lindenberg, DR Weinberger, ... PLoS computational biology 6 (4), e1000748, 2010	414	2010
The CHERI capability model: Revisiting RISC in an age of risk J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... ACM SIGARCH Computer Architecture News 42 (3), 457-468, 2014	309	2014
Improving smart card security using self-timed circuits S Moore, R Anderson, P Cunningham, R Mullins, G Taylor Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002	275	2002
CHERI: A hybrid capability-system architecture for scalable software compartmentalization RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ... 2015 IEEE Symposium on Security and Privacy, 20-37, 2015	255	2015
A communication characterisation of splash-2 and parsec N Barrow-Williams, C Fensch, S Moore 2009 IEEE international symposium on workload characterization (IISWC), 86-97, 2009	244	2009
The frequency injection attack on ring-oscillator-based true random number generators AT Markettos, SW Moore Cryptographic Hardware and Embedded Systems-CHES 2009: 11th International …, 2009	208	2009
Point to point GALS interconnect S Moore, G Taylor, R Mullins, P Robinson Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002	186	2002
The design and implementation of a low-latency on-chip network R Mullins, A West, S Moore Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006	175	2006
A power and energy exploration of network-on-chip architectures A Banerjee, R Mullins, S Moore First International Symposium on Networks-on-Chip (NOCS'07), 163-172, 2007	143	2007
Balanced self-checking asynchronous logic for smart card applications S Moore, R Anderson, R Mullins, G Taylor, JJA Fournier Microprocessors and Microsystems 27 (9), 421-430, 2003	135	2003
Security evaluation of asynchronous circuits JJA Fournier, S Moore, H Li, R Mullins, G Taylor Cryptographic Hardware and Embedded Systems-CHES 2003: 5th International …, 2003	128	2003
Bluehive-a field-programable custom computing machine for extreme-scale real-time neural network simulation SW Moore, PJ Fox, SJT Marsh, AT Markettos, A Mujumdar 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012	125	2012
Beyond the PDP-11: Architectural support for a memory-safe C abstract machine D Chisnall, C Rothwell, RNM Watson, J Woodruff, M Vadera, SW Moore, ... ACM SIGARCH Computer Architecture News 43 (1), 117-130, 2015	103	2015
Demystifying data-driven and pausible clocking schemes R Mullins, S Moore 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007	93	2007
Self calibrating clocks for globally asynchronous locally synchronous systems SW Moore, GS Taylor, PA Cunningham, RD Mullins, P Robinson Proceedings 2000 International Conference on Computer Design, 73-78, 2000	93	2000
An energy and performance exploration of network-on-chip architectures A Banerjee, PT Wolkotte, RD Mullins, SW Moore, GJM Smit IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 319-329, 2009	88	2009
Security evaluation against electromagnetic analysis at design time H Li, AT Markettos, S Moore Tenth IEEE International High-Level Design Validation and Test Workshop …, 2005	82	2005
Implications of Rent's rule for NoC design and its fault-tolerance D Greenfield, A Banerjee, JG Lee, S Moore First International Symposium on Networks-on-Chip (NOCS'07), 283-294, 2007	77	2007
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019	72	2019

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