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Hyunyoon Cho
Hyunyoon Cho
Samsung electronics
Zweryfikowany adres z snu.ac.kr
Tytuł
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Cytowane przez
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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 128 I/Os Using TSV Based Stacking
JS Kim, CS Oh, H Lee, D Lee, HR Hwang, S Hwang, B Na, J Moon, ...
IEEE Journal of Solid-State Circuits 47 (1), 107-116, 2011
3702011
Defect analysis and cost-effective resilience architecture for future DRAM devices
S Cha, O Seongil, H Shin, S Hwang, K Park, SJ Jang, JS Choi, GY Jin, ...
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
462017
A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
YC Bae, JY Park, SJ Rhee, SB Ko, Y Jeong, KS Noh, Y Son, J Youn, ...
2012 IEEE International Solid-State Circuits Conference, 44-46, 2012
452012
Leveraging Power-performance Relationship of Energy-efficient Modern DRAM Devices
JHA Sukhan Lee, Hyunyoon Cho, Young Hoon Son, Yuhwan Ro, Nam Sung Kim
IEEE Access, 2018
172018
23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power
KS Ha, CK Lee, D Lee, D Moon, JH Jang, HR Hwang, H Chi, J Park, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 378-380, 2019
142019
22.2 An 8.5 Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
HJ Chi, CK Lee, J Park, JS Heo, J Jung, D Lee, DH Kim, D Park, K Kim, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 382-384, 2020
62020
SALAD: Achieving symmetric access latency with asymmetric DRAM architecture
YH Son, H Cho, Y Ro, JW Lee, JH Ahn
IEEE Computer Architecture Letters 16 (1), 76-79, 2016
52016
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures
Y Ro, H Cho, E Lee, D Jung, YH Son, JH Ahn, JW Lee
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
42017
Understanding power-performance relationship of energy-efficient modern DRAM devices
S Lee, Y Ro, YH Son, H Cho, NS Kim, JH Ahn
2017 IEEE International Symposium on Workload Characterization (IISWC), 110-111, 2017
32017
Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM
CK Lee, J Lee, KH Kim, JS Heo, GH Cha, JH Baek, DS Moon, YJ Eom, ...
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 153-156, 2017
22017
A 1.2 V 12.8 GB/s 2Gb mobile wide-i/o dram with 4x l 28 ii0s using tsv-based stacking
JS Kim, C Oh, H Lee, D Lee, HR Hwang
International Solid-State Circuits Conference, 2011
22011
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE
H Jin, J Byun, H Cho, H Yoon, JH Park, K Kim, Y Choi, JH Choi, H Ko, ...
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021
12021
TRANSLATION DEVICE, TEST SYSTEM INCLUDING THE SAME, AND MEMORY SYSTEM INCLUDING THE TRANSLATION DEVICE
H Jin, Y Son, H Cho, Y Choi, J Choi
US Patent App. 17/366,329, 2022
2022
Memory device and memory system
JY Park, SON Young-Hoon, HY Cho, YD Choi, JH Choi
US Patent App. 17/398,158, 2022
2022
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process
J Kim, J Park, J Byun, C Seol, CS Yoon, ES Shin, H Cho, Y Um, S Lee, ...
2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022
2022
Memory device for generating pulse amplitude modulation-based dq signal and memory system including the same
Y Um, SON YoungHoon, C Youngdon, B Jindo, H Cho, J Choi
US Patent App. 17/385,002, 2022
2022
Memory devices configured to generate pulse amplitude modulation-based dq signals, memory controllers, and memory systems including the memory devices and the memory controllers
SC Lee, SON YoungHoon, H Cho, C Youngdon, J Choi
US Patent App. 17/347,998, 2022
2022
Memory device, controller controlling the same, memory system including the same, and operating method thereof
H Cho, S Cho, SON YoungHoon, C Youngdon, J Choi
US Patent App. 17/229,055, 2022
2022
Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same
J Park, SON YoungHoon, H Cho, C Youngdon, J Choi
US Patent App. 17/321,678, 2022
2022
Clock converting circuit with symmetric structure
J Park, SON Young-Hoon, HY Cho, C Youngdon, J Choi
US Patent App. 17/145,211, 2021
2021
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