Obserwuj
John P Hayes
Tytuł
Cytowane przez
Cytowane przez
Rok
Computer Architecture and Organization
JP Hayes
McGraw-Hill, 1978
994*1978
Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering
MC Hansen, H Yalcin, JP Hayes
IEEE Design & Test of Computers 16 (3), 72-80, 1999
6221999
Synthesis of reversible logic circuits
VV Shende, AK Prasad, IL Markov, JP Hayes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
5982003
Survey of stochastic computing
A Alaghi, JP Hayes
ACM Transactions on Embedded computing systems (TECS) 12 (2s), 1-19, 2013
5392013
A survey of the theory of hypercube graphs
F Harary, JP Hayes, HJ Wu
Computers & Mathematics with Applications 15 (4), 277-289, 1988
4331988
A graph model for fault-tolerant computing systems
JP Hayes
IEEE Transactions on Computers 25 (09), 875-884, 1976
4041976
Accurate reliability evaluation and enhancement via probabilistic transfer matrices
S Krishnaswamy, GF Viamontes, IL Markov, JP Hayes
Design, Automation and Test in Europe, 282-287, 2005
3642005
Architecture of a Hypercube Supercomputer.
JP Hayes, TN Mudge, QF Stout, S Colley, J Palmer
ICPP, 653-660, 1986
2981986
Hierarchical test generation using precomputed tests for modules
BT Murray, JP Hayes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990
2711990
A microprocessor-based hypercube supercomputer
JP Hayes, T Mudge, QF Stout, S Colley, J Palmer
IEEE micro 6 (5), 6-17, 1986
2701986
Stochastic circuits for real-time image-processing applications
A Alaghi, C Li, JP Hayes
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
2652013
Fault testing for reversible circuits
KN Patel, JP Hayes, IL Markov
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
2292004
A fault-tolerant communication scheme for hypercube computers
TC Lee, JP Hayes
IEEE Transactions on Computers 41 (10), 1242-1256, 1992
2201992
Hypercube supercomputers
JP Hayes, T Mudge
Proceedings of the IEEE 77 (12), 1829-1841, 1989
2171989
Introduction to digital logic design
BNOT Gate, GN Gate, UILIO Upper, OR Gate, NOR Gate, XOR Gate, ...
2091993
Reversible logic circuit synthesis
VV Shende, AK Prasad, IL Markov, JP Hayes
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
2052002
Low-cost on-line fault detection using control flow assertions
R Venkatasubramanian, JP Hayes, BT Murray
9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 137-143, 2003
1912003
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-CMOS
JY Chen, MP Flynn, JP Hayes
IEEE Journal of Solid-State Circuits 42 (9), 1976-1985, 2007
1832007
Transition count testing of combinational logic circuits
JP Hayes
IEEE Transactions on Computers 25 (06), 613-620, 1976
1741976
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
S Krishnaswamy, GF Viamontes, IL Markov, JP Hayes
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008
1632008
Nie można teraz wykonać tej operacji. Spróbuj ponownie później.
Prace 1–20