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Yi-Chen Lu
Tytuł
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GAN-CTS: A generative adversarial framework for clock tree prediction and optimization
YC Lu, J Lee, A Agnesina, K Samadi, SK Lim
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
742019
TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs
YC Lu, SSK Pentapati, L Zhu, K Samadi, SK Lim
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
672020
Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning
YC Lu, S Nath, V Khandelwal, SK Lim
2021 58th ACM/IEEE Design Automation Conference (DAC), 733-738, 2021
402021
The law of attraction: Affinity-aware placement optimization using graph neural networks
YC Lu, S Pentapati, SK Lim
Proceedings of the 2021 International Symposium on Physical Design, 7-14, 2021
352021
VLSI placement optimization using graph neural networks
YC Lu, S Pentapati, SK Lim
Proceedings of the 34th Advances in Neural Information Processing Systems …, 2020
232020
Placement optimization via ppa-directed graph clustering
YC Lu, T Yang, SK Lim, H Ren
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 1-6, 2022
172022
Doomed run prediction in physical design by exploiting sequential flow and graph learning
YC Lu, S Nath, V Khandelwal, SK Lim
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
172021
Snap-3D: A constrained placement-driven physical design methodology for face-to-face-bonded 3D ICs
P Vanna-Iampikul, C Shao, YC Lu, S Pentapati, SK Lim
Proceedings of the 2021 International Symposium on Physical Design, 39-46, 2021
162021
A fast learning-driven signoff power optimization framework
YC Lu, S Nath, SSK Pentapati, SK Lim
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
152020
A machine learning-powered tier partitioning methodology for monolithic 3-D ICs
YC Lu, S Pentapati, L Zhu, G Murali, K Samadi, SK Lim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
102021
On advancing physical design using graph neural networks
YC Lu, SK Lim
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
92022
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *
SC Hung, YC Lu, SK Lim, K Chakrabarty
2020 IEEE 29th Asian Test Symposium (ATS), 1-6, 2020
92020
Eco-gnn: Signoff power prediction using graph neural networks with subgraph approximation
YC Lu, S Nath, S Pentapati, SK Lim
ACM Transactions on Design Automation of Electronic Systems 28 (4), 1-22, 2023
72023
Driving early physical synthesis exploration through end-of-flow total power prediction
YC Lu, WT Chan, V Khandelwal, SK Lim
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 97-102, 2022
72022
RL-CCD: Concurrent clock and data optimization using attention-based self-supervised reinforcement learning
YC Lu, WT Chan, D Guo, S Kundu, V Khandelwal, SK Lim
2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023
62023
DREAM-GAN: Advancing dreamplace towards commercial-quality using generative adversarial learning
YC Lu, H Ren, HH Hsiao, SK Lim
Proceedings of the 2023 International Symposium on Physical Design, 141-148, 2023
52023
Power supply noise-aware at-speed delay fault testing of monolithic 3-D ICs
SC Hung, YC Lu, SK Lim, K Chakrabarty
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (11 …, 2021
52021
Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning. In 2021 58th ACM/IEEE Design Automation Conference (DAC)
YC Lu, S Nath, V Khandelwal, SK Lim
IEEE, 733ś738, 2021
52021
A fast learningdriven signoff power optimization framework. In 2020 IEEE
YC Lu, S Nath, SSK Pentapati, SK Lim
ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2020
52020
Doomed run prediction in physical design by exploiting sequential flow and graph learning. In 2021 IEEE
YC Lu, S Nath, V Khandelwal, SK Lim
ACM International Conference On Computer Aided Design (ICCAD), 1-9, 0
5
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