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Kiyoung Choi
Kiyoung Choi
Seoul National University, Department of Electrical and Computer Engineering
Zweryfikowany adres z snu.ac.kr - Strona główna
Tytuł
Cytowane przez
Cytowane przez
Rok
A scalable processing-in-memory accelerator for parallel graph processing
J Ahn, S Hong, S Yoo, O Mutlu, K Choi
Computer Architecture (ISCA), 2015 ACM/IEEE 42nd Annual International …, 2015
7692015
Power conscious fixed priority scheduling for hard real-time systems
Y Shin, K Choi
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 134-139, 1999
4971999
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture
J Ahn, S Yoo, O Mutlu, K Choi
2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture …, 2015
4672015
Power optimization of real-time embedded systems on variable speed processors
Y Shin, K Choi, T Sakurai
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided …, 2000
3622000
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks
K Kim, J Kim, J Yu, J Seo, J Lee, K Choi
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
1792016
Partial bus-invert coding for power optimization of application-specific systems
Y Shin, SI Chae, K Choi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (2), 377-383, 2001
1462001
Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization
Y Kim, M Kiemb, C Park, J Jung, K Choi
Design, Automation and Test in Europe, 12-17, 2005
1272005
Power minimization of functional units partially guarded computation
J Choi, J Jeon, K Choi
Proceedings of the 2000 international symposium on Low power electronics and …, 2000
1242000
Compilation approach for coarse-grained reconfigurable architectures
J Lee, K Choi, ND Dutt
IEEE Design & Test of Computers 20 (1), 26-33, 2003
1142003
Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array
A Rahman, J Lee, K Choi
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
1072016
DASCA: Dead write prediction assisted STT-RAM cache architecture
J Ahn, S Yoo, K Choi
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
1062014
Partial bus-invert coding for power optimization of system level bus
Y Shin, SIK Chae, K Choi
Proceedings of the 1998 international symposium on Low power electronics and …, 1998
1021998
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
J Lee, K Choi, N Dutt
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
822002
Behavior-to-placed RTL synthesis with performance-driven placement
D Kim, J Jung, S Lee, J Jeon, K Choi
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001
762001
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures
M Ahn, JW Yoon, Y Paek, Y Kim, M Kiemb, K Choi
Proceedings of the Design Automation & Test in Europe Conference 1, 6 pp., 2006
742006
An algorithm for mapping loops onto coarse-grained reconfigurable architectures
J Lee, K Choi, ND Dutt
ACM Sigplan Notices 38 (7), 183-188, 2003
742003
Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture
M Jo, VKP Arava, H Yang, K Choi
2007 IEEE International SOC Conference, 127-130, 2007
702007
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
Y Kim, I Park, K Choi, Y Paek
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
702006
Deep neural networks with weighted spikes
J Kim, H Kim, S Huh, J Lee, K Choi
Neurocomputing 311, 373-386, 2018
692018
Semiconductor memory device including non-volatile memory, cache memory, and computer system
S Kim, HM Kwon, YJ Kwon, K Choi, J Ahn
US Patent 9,250,997, 2016
652016
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