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Alfio Di Mauro
Alfio Di Mauro
Integrated System Laboratory, ETH Zurich
Verified email at iis.ee.ethz.ch
Title
Cited by
Cited by
Year
Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing
A Pullini, D Rossi, I Loi, A Di Mauro, L Benini
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
402018
Quentin: an ultra-low-power pulpissimo soc in 22nm fdx
PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
262018
Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3905-3918, 2020
202020
4.4 A 1.3 TOPS/W@ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7 μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021
172021
Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: A low-power accelerator with online learning capability
M Hersche, EM Rella, A Di Mauro, L Benini, A Rahimi
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
112020
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ...
IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021
102021
Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes
PD Schiavone, D Rossi, A Di Mauro, FK Gürkaynak, T Saxe, M Wang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 677-690, 2021
102021
An ultra-low power address-event sensor interface for energy-proportional time-to-information extraction
A Di Mauro, F Conti, L Benini
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2017
62017
Pushing on-chip memories beyond reliability boundaries in micropower machine learning applications
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
2019 IEEE International Electron Devices Meeting (IEDM), 30.4. 1-30.4. 4, 2019
52019
Independent body-biasing of pn transistors in an 28nm utbb fd-soi ulp near-threshold multi-core cluster
A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
52018
Quentin: an ultra-low-power pulpissimo soc in 22nm fdx. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini
IEEE, 2018
42018
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology
A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
42017
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
A Garofalo, G Ottavi, A Di Mauro, F Conti, G Tagliavini, L Benini, D Rossi
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
32021
Live demonstration: Exploiting body-biasing for static corner trimming and maximum energy efficiency operation in 22nm FDX technology
A Di Mauro, F Zaruba, F Schuiki, S Mach, L Benini
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2020
32020
Towards always-on event-based cameras for long-lasting battery-operated smart sensor nodes
M Scherer, P Mayer, A Di Mauro, M Magno, L Benini
2021 IEEE International Instrumentation and Measurement Technology …, 2021
22021
An energy-efficient low-voltage swing transceiver for mW-range IoT end-nodes
H Okuhara, A Elnaqib, D Rossi, A Di Mauro, P Mayer, P Palestri, L Benini
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
22020
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI
A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini
Integration 72, 194-207, 2020
22020
Idleness-Aware Dynamic Power Mode Selection on the i.MX 7ULP IoT Edge Processor
A Di Mauro, H Fatemi, JP de Gyvez, Benini
JLPEA, 2020
22020
A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications
M Scherer, A Di Mauro, G Rutishauser, T Fischer, L Benini
2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2022
12022
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
G Ottavi, A Garofalo, G Tagliavini, F Conti, A Di Mauro, L Benini, D Rossi
arXiv preprint arXiv:2201.08656, 2022
12022
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