| CACTI: An enhanced cache access and cycle time model SJE Wilton, NP Jouppi IEEE Journal of solid-state circuits 31 (5), 677-688, 1996 | 1079 | 1996 |
| Reconfigurable computing: architectures and design methods TJ Todman, GA Constantinides, SJE Wilton, O Mencer, W Luk, ... IEE Proceedings-Computers and Digital Techniques 152 (2), 193-207, 2005 | 594 | 2005 |
| An enhanced access and cycle time model for on-chip caches SJE Wilton WRL Research Report, 1994 | 501 | 1994 |
| System-on-chip: Reuse and integration R Saleh, S Wilton, S Mirabbasi, A Hu, M Greenstreet, G Lemieux, ... Proceedings of the IEEE 94 (6), 1050-1069, 2006 | 403 | 2006 |
| Architectures and algorithms for field-programmable gate arrays with embedded memory SJE Wilton University of Toronto, 1997 | 263 | 1997 |
| A detailed power model for field-programmable gate arrays KKW Poon, SJE Wilton, A Yan ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (2 …, 2005 | 233 | 2005 |
| Tradeoffs in two-level on-chip caching NP Jouppi, SJE Wilton ACM SIGARCH Computer Architecture News 22 (2), 34-45, 1994 | 230 | 1994 |
| A flexible power model for FPGAs KKW Poon, A Yan, SJE Wilton International Conference on Field Programmable Logic and Applications, 312-321, 2002 | 223 | 2002 |
| On the interaction between power-aware FPGA CAD algorithms J Lamoureux, SJE Wilton ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 195 | 2003 |
| Dynamic voltage scaling for commercial FPGAs CT Chow, LSM Tsui, PHW Leong, W Luk, SJE Wilton Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005 | 162 | 2005 |
| The impact of pipelining on energy per operation in field-programmable gate arrays SJE Wilton, SS Ang, W Luk Field Programmable Logic and Application: 14th International Conference, FPL …, 2004 | 144 | 2004 |
| Memory-to-memory connection structures in FPGAs with embedded memory arrays SJE Wilton, J Rose, ZG Vranesic Proceedings of the 1997 ACM fifth international symposium on Field …, 1997 | 131 | 1997 |
| Activity estimation for field-programmable gate arrays J Lamoureux, SJE Wilton 2006 International Conference on Field Programmable Logic and Applications, 1-8, 2006 | 124 | 2006 |
| Backspace: Formal analysis for post-silicon debug FM De Paula, M Gort, AJ Hu, SJE Wilton, J Yang 2008 Formal Methods in Computer-Aided Design, 1-10, 2008 | 108 | 2008 |
| Floating-point FPGA: Architecture and modeling CH Ho, CW Yu, P Leong, W Luk, SJE Wilton IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (12 …, 2009 | 98 | 2009 |
| Programmable logic IP cores in SoC design: Opportunities and challenges SJE Wilton, R Saleh Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No …, 2001 | 95 | 2001 |
| A new switch block for segmented FPGAs MI Masud, SJE Wilton Field Programmable Logic and Applications: 9th International Workshop, FPL …, 1999 | 92 | 1999 |
| LeFlow: Enabling flexible FPGA high-level synthesis of tensorflow deep neural networks DH Noronha, B Salehpour, SJE Wilton FSP Workshop 2018; Fifth International Workshop on FPGAs for Software …, 2018 | 89 | 2018 |
| An energy and power consumption analysis of FPGA routing architectures P Jamieson, W Luk, SJE Wilton, GA Constantinides 2009 International Conference on Field-Programmable Technology, 324-327, 2009 | 83 | 2009 |
| SMAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays SJE Wilton Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field …, 1998 | 81 | 1998 |
