| Single-chip microprocessor that communicates directly using light C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ... Nature 528 (7583), 534-538, 2015 | 1374 | 2015 |
| The rocket chip generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 854 | 2016 |
| CudaDMA: optimizing GPU memory bandwidth via warp specialization M Bauer, H Cook, B Khailany Proceedings of 2011 international conference for high performance computing …, 2011 | 216 | 2011 |
| RAMP gold: an FPGA-based architecture simulator for multiprocessors Z Tan, A Waterman, R Avizienis, Y Lee, H Cook, D Patterson, K Asanović Proceedings of the 47th Design Automation Conference, 463-468, 2010 | 183 | 2010 |
| A 45nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators Y Lee, A Waterman, R Avizienis, H Cook, C Sun, V Stojanović, K Asanović ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 199-202, 2014 | 180 | 2014 |
| A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness H Cook, M Moreto, S Bird, K Dao, DA Patterson, K Asanovic ACM SIGARCH Computer Architecture News 41 (3), 308-319, 2013 | 171 | 2013 |
| An agile approach to building RISC-V microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... ieee Micro 36 (2), 8-20, 2016 | 163 | 2016 |
| The rocket chip generator. EECS Department K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4, 6-2, 2016 | 153 | 2016 |
| A case for FAME: FPGA architecture model execution Z Tan, A Waterman, H Cook, S Bird, K Asanović, D Patterson Proceedings of the 37th annual international symposium on Computer …, 2010 | 117 | 2010 |
| Virtual local stores: Enabling software-managed memory hierarchies in mainstream computing environments H Cook, K Asanovic, DA Patterson Technical Report No. UCB/EECS-2009-131, 2009 | 110 | 2009 |
| Resource management in the Tessellation manycore OS JA Colmenares, S Bird, H Cook, P Pearce, D Zhu, J Shalf, S Hofmeyr, ... HotPar10, Berkeley, CA, 2010 | 62 | 2010 |
| Diplomatic design patterns: A TileLink case study H Cook, W Terpstra, Y Lee 1st Workshop on Computer Architecture Research with RISC-V 23, 2017 | 52 | 2017 |
| Predictive design space exploration using genetically programmed response surfaces H Cook, K Skadron Proceedings of the 45th Annual Design Automation Conference, 960-965, 2008 | 52 | 2008 |
| The RISC-V instruction set. A Waterman, Y Lee, R Avizienis, H Cook, DA Patterson, K Asanovic Hot Chips Symposium 1, 2013 | 37 | 2013 |
| Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015 | 24 | 2015 |
| Portable parallel performance from sequential, productive, embedded domain-specific languages S Kamil, D Coetzee, S Beamer, H Cook, E Gonina, J Harper, J Morlan, ... ACM SIGPLAN Notices 47 (8), 303-304, 2012 | 24 | 2012 |
| Fast speaker diarization using a high-level scripting language E Gonina, G Friedland, H Cook, K Keutzer 2011 IEEE Workshop on Automatic Speech Recognition & Understanding, 553-558, 2011 | 21 | 2011 |
| Productive design of extensible on-chip memory hierarchies HM Cook University of California, Berkeley, 2016 | 18 | 2016 |
| {CUDA-level} Performance with Python-level Productivity for Gaussian Mixture Model Applications H Cook, E Gonina, S Kamil, G Friedland, D Patterson, A Fox 3rd USENIX Workshop on Hot Topics in Parallelism (HotPar 11), 2011 | 15 | 2011 |
| Iotafs: Exploring file system optimizations for ssds H Cook, J Ellithorpe, L Keys, A Waterman University of California at Berkeley, 2008 | 8 | 2008 |
