Kailash Gopalakrishnan
Kailash Gopalakrishnan
Zweryfikowany adres z us.ibm.com
Cytowane przez
Cytowane przez
Deep learning with limited numerical precision
S Gupta, A Agrawal, K Gopalakrishnan, P Narayanan
International conference on machine learning, 1737-1746, 2015
Phase change memory technology
GW Burr, MJ Breitwisch, M Franceschini, D Garetto, K Gopalakrishnan, ...
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2010
Overview of candidate device technologies for storage-class memory
GW Burr, BN Kurdi, JC Scott, CH Lam, K Gopalakrishnan, RS Shenoy
IBM Journal of Research and Development 52 (4.5), 449-464, 2008
I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q
K Gopalakrishnan, PB Griffin, JD Plummer
Digest. International Electron Devices Meeting,, 289-292, 2002
Pact: Parameterized clipping activation for quantized neural networks
J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ...
arXiv preprint arXiv:1805.06085, 2018
Activation and diffusion studies of ion-implanted and dopants in germanium
CO Chui, K Gopalakrishnan, PB Griffin, JD Plummer, KC Saraswat
Applied physics letters 83 (16), 3275-3277, 2003
Impact ionization MOS (I-MOS)-Part I: device and circuit simulations
K Gopalakrishnan, PB Griffin, JD Plummer
IEEE Transactions on electron devices 52 (1), 69-76, 2004
Training deep neural networks with 8-bit floating point numbers
N Wang, J Choi, D Brand, CY Chen, K Gopalakrishnan
Proceedings of the 32nd International Conference on Neural Information …, 2018
Nanoscale electronic synapses using phase change devices
BL Jackson, B Rajendran, GS Corrado, M Breitwisch, GW Burr, R Cheek, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (2), 1-20, 2013
Specifications of nanoscale devices and circuits for neuromorphic computational systems
B Rajendran, Y Liu, J Seo, K Gopalakrishnan, L Chang, DJ Friedman, ...
IEEE Transactions on Electron Devices 60 (1), 246-253, 2012
Impact ionization MOS (I-MOS)-part II: experimental results
K Gopalakrishnan, R Woo, C Jungemann, PB Griffin, JD Plummer
IEEE Transactions on Electron Devices 52 (1), 77-84, 2004
Rectifying element for a crosspoint based memory array architecture
K Gopalakrishnan
US Patent 8,203,873, 2012
Rectifying element for a crosspoint based memory array architecture
K Gopalakrishnan
US Patent 7,382,647, 2008
Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays
K Gopalakrishnan, RS Shenoy, CT Rettner, K Virwani, DS Bethune, ...
2010 Symposium on VLSI Technology, 205-206, 2010
Adacomp: Adaptive residual gradient compression for data-parallel distributed training
CY Chen, J Choi, D Brand, A Agrawal, W Zhang, K Gopalakrishnan
Proceedings of the AAAI Conference on Artificial Intelligence 32 (1), 2018
A scalable multi-TeraOPS deep learning processor core for AI trainina and inference
B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ...
2018 IEEE Symposium on VLSI Circuits, 35-36, 2018
Accurate and Efficient 2-bit Quantized Neural Networks.
J Choi, S Venkataramani, V Srinivasan, K Gopalakrishnan, Z Wang, ...
MLSys, 2019
Approximate computing: Challenges and opportunities
A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, J Oh, DA Prener, ...
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks
X Sun, J Choi, CY Chen, N Wang, S Venkataramani, X Cui, W Zhang, ...
Method and structure for increasing effective transistor width in memory arrays with dual bitlines
GW Burr, K Gopalakrishnan
US Patent 7,447,062, 2008
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