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Dylan Stow
Dylan Stow
Senior Design Engineer at AMD
Zweryfikowany adres z amd.com - Strona główna
Tytuł
Cytowane przez
Cytowane przez
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Cost-Effective Design of Scalable High-Performance Systems Using Active and Passive Interposers
D Stow, Y Xie, T Siddiqua, GH Loh
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 728-735, 2017
652017
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5 D/3D integration
D Stow, I Akgun, R Barnes, P Gu, Y Xie
Proceedings of the 35th International Conference on Computer-Aided Design …, 2016
402016
Leveraging 3d technologies for hardware security: Opportunities and challenges
P Gu, S Li, D Stow, R Barnes, L Liu, Y Xie, E Kursun
Great Lakes Symposium on VLSI (GLSVLSI), 2016 International, 347-352, 2016
362016
Die stacking is happening
X Hu, D Stow, Y Xie
IEEE micro 38 (1), 22-28, 2018
232018
Thermal-aware 3D design for side-channel information leakage
P Gu, D Stow, R Barnes, E Kursun, Y Xie
2016 IEEE 34th International Conference on Computer Design (ICCD), 520-527, 2016
202016
Security threats and countermeasures in three-dimensional integrated circuits
J Dofe, P Gu, D Stow, Q Yu, E Kursun, Y Xie
Proceedings of the on Great Lakes Symposium on VLSI 2017, 321-326, 2017
172017
Cost and thermal analysis of high-performance 2.5 D and 3D integrated circuit design space
D Stow, I Akgun, R Barnes, P Gu, Y Xie
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 637-642, 2016
132016
Cost-efficient 3D integration to hinder reverse engineering during and after manufacturing
P Gu, D Stow, P Mukim, S Li, Y Xie
2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 74-79, 2018
102018
Efficient system architecture in the era of monolithic 3D: Dynamic inter-tier interconnect and processing-in-memory
D Stow, I Akgun, W Huangfu, Y Xie, X Li, GH Loh
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019
72019
Investigation of cost-optimal network-on-chip for passive and active interposer systems
D Stow, I Akgun, Y Xie
2019 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2019
72019
Network-on-chip design guidelines for monolithic 3-D integration
I Akgun, D Stow, Y Xie
IEEE Micro 39 (6), 46-53, 2019
62019
Yield-driven minimum energy CMOS cell design
MA Korbel, DC Stow, CR Ferguson, DM Harris
2012 Conference Record of the Forty Sixth Asilomar Conference on Signals …, 2012
32012
Power profiling of modern die-stacked memory
D Stow, A Farmahini-Farahani, S Gurumurthi, M Ignatowski, Y Xie
IEEE Computer Architecture Letters 18 (2), 132-135, 2019
12019
Cost-Driven Integration Architectures for Multi-Die Silicon Systems
DS Randall
University of California, Santa Barbara, 2020
2020
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