| Scenario-based design flow for mapping streaming applications onto on-chip many-core systems L Schor, I Bacivarov, D Rai, H Yang, SH Kang, L Thiele Proceedings of the 2012 international conference on Compilers, architectures …, 2012 | 142 | 2012 |
| 25.4 a 20nm 6gb function-in-memory dram, based on hbm2 with a 1.2 tflops programmable computing unit using bank-level parallelism, for machine learning applications YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021 | 46 | 2021 |
| Multi-objective mapping optimization via problem decomposition for many-core systems SH Kang, H Yang, L Schor, I Bacivarov, S Ha, L Thiele 2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 28-37, 2012 | 44 | 2012 |
| Static mapping of mixed-critical applications for fault-tolerant MPSoCs S Kang, H Yang, S Kim, I Bacivarov, S Ha, L Thiele Proceedings of the 51st annual design automation conference, 1-6, 2014 | 41 | 2014 |
| Dynamic behavior specification and dynamic mapping for real-time embedded systems: Hopes approach H Jung, C Lee, SH Kang, S Kim, H Oh, S Ha ACM Transactions on Embedded Computing Systems (TECS) 13 (4s), 1-26, 2014 | 37 | 2014 |
| Hardware architecture and software stack for PIM based on commercial DRAM technology: Industrial product S Lee, S Kang, J Lee, H Kim, E Lee, S Seo, H Yoon, S Lee, K Lim, H Shin, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 26 | 2021 |
| Reliability-aware mapping optimization of multi-core systems with mixed-criticality SH Kang, H Yang, S Kim, I Bacivarov, S Ha, L Thiele 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 26 | 2014 |
| An ILP-based worst-case performance analysis technique for distributed real-time embedded systems J Kim, H Oh, H Ha, SH Kang, J Choi, S Ha 2012 IEEE 33rd Real-Time Systems Symposium, 363-372, 2012 | 18 | 2012 |
| TQSIM: A fast cycle-approximate processor simulator based on QEMU S Kang, D Yoo, S Ha Journal of Systems Architecture 66, 33-47, 2016 | 17 | 2016 |
| Near-memory processing in action: Accelerating personalized recommendation with AxDIMM L Ke, X Zhang, J So, JG Lee, SH Kang, S Lee, S Han, YG Cho, JH Kim, ... IEEE Micro 42 (1), 116-127, 2021 | 11 | 2021 |
| Real-time co-scheduling of multiple dataflow graphs on multi-processor systems S Kang, D Kang, H Yang, S Ha Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 9 | 2016 |
| Optimal checkpoint selection with dual-modular redundancy hardening SH Kang, H Park, S Kim, H Oh, S Ha IEEE Transactions on Computers 64 (7), 2036-2048, 2014 | 8 | 2014 |
| 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2 TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. In 2021 … YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ... IEEE, 2021 | 6 | 2021 |
| Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond JH Kim, S Kang, S Lee, H Kim, W Song, Y Ro, S Lee, D Wang, H Shin, ... 2021 IEEE Hot Chips 33 Symposium (HCS), 1-26, 2021 | 3 | 2021 |
| Fast parallel simulation of a manycore architecture with a flit-level on-chip network model S Kang, J Kang, S Ha Proceedings of the 18th International Conference on Embedded Computer …, 2018 | 2 | 2018 |
| Memory device for performing in-memory processing Y Ro, K Shinhaeng, O Seongil, S Seo US Patent App. 17/314,476, 2022 | | 2022 |
| Aquabolt-XL HBM2-PIM, LPDDR5-PIM with in-memory processing, and AXDIMM with acceleration buffer JH Kim, S Kang, S Lee, H Kim, Y Ro, S Lee, D Wang, J Choi, J So, ... IEEE Micro, 2022 | | 2022 |
| An FPGA-based RNN-T Inference Accelerator with PIM-HBM S Kang, S Lee, B Kim, H Kim, K Sohn, NS Kim, E Lee Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | | 2022 |
| Memory device for performing in-memory processing Y Ro, K Shinhaeng, S Park, S Seo US Patent App. 17/098,959, 2021 | | 2021 |
Lothar ThieleProfessor of Computer Engineering, ETH ZurichZweryfikowany adres z ethz.ch
