| CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques S Li, K Chen, JH Ahn, JB Brockman, NP Jouppi Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on …, 2011 | 256 | 2011 |
| CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory K Chen, S Li, N Muralimanohar, JH Ahn, JB Brockman, NP Jouppi Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, 33-38, 2012 | 230 | 2012 |
| CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. In 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). 33–38 K Chen, S Li, N Muralimanohar, JH Ahn, JB Brockman, NP Jouppi | 230* | 2012 |
| Half-DRAM: a High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation T Zhang, K Chen, C Xu, G Sun, T Wang, Y Xie Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014 | 129 | 2014 |
| System implications of memory reliability in exascale computing S Li, K Chen, MY Hsieh, N Muralimanohar, CD Kersey, JB Brockman, ... Proceedings of 2011 International Conference for High Performance Computing …, 2011 | 66 | 2011 |
| MAGE: adaptive granularity and ECC for resilient and power efficient memory systems S Li, DH Yoon, K Chen, J Zhao, JH Ahn, JB Brockman, Y Xie, NP Jouppi High Performance Computing, Networking, Storage and Analysis (SC), 2012 …, 2012 | 36 | 2012 |
| 3D-SWIFT: a High-performance 3D-stacked Wide IO DRAM T Zhang, C Xu, K Chen, G Sun, Y Xie Proceedings of the 24th edition of the great lakes symposium on VLSI, 51-56, 2014 | 23 | 2014 |
| Performance impacts of non-blocking caches in out-of-order processors S Li, K Chen, JB Brockman, NP Jouppi Technical paper, 2011 | 15 | 2011 |
| Crail-KV: A High-Performance Distributed Key-Value Store Leveraging Native KV-SSDs over NVMe-oF T Bisson, K Chen, C Choi, V Balakrishnan, Y Kee 2018 IEEE 37th International Performance Computing and Communications …, 2018 | 11 | 2018 |
| History-Assisted Adaptive-Granularity Caches (HAAG $) for High Performance 3D DRAM Architectures K Chen, S Li, JH Ahn, N Muralimanohar, J Zhao, C Xu, Y Xie, ... Proceedings of the 29th ACM on International Conference on Supercomputing …, 2015 | 3 | 2015 |
| System Implications of Memory Reliability in Exascale Computing. MNMN Hsieh, AF Rodrigues, S Li, K Chen, N Muralimanohar, CD Kersey, ... Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States), 2011 | 1 | 2011 |
| Separate memory controllers to access data in memory DH Yoon, S Li, J Chang, K Chen, P Ranganathan, NP Jouppi US Patent App. 14/785,120, 2016 | | 2016 |
| Caching data in a memory system having memory nodes at different hierarchical levels NP Jouppi, S Li, K Chen US Patent App. 14/764,651, 2015 | | 2015 |
| Modeling and design of high-performance and power-efficient 3D dram architectures K Chen University of Notre Dame, 2013 | | 2013 |
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