Jaan Raik
Jaan Raik
Tallinn University of Technology
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Cited by
Cited by
Design and test technology for dependable systems-on-chip
R Ubar, J Raik, HT Vierhaus
IGI Global, 2011
Fast test pattern generation for sequential circuits using decision diagram representations
J Raik, R Ubar
Journal of Electronic Testing 16 (3), 213-226, 2000
An external test approach for network-on-a-chip switches
J Raik, V Govind, R Ubar
2006 15th Asian Test Symposium, 437-442, 2006
Test configurations for diagnosing faulty links in NoC switches
J Raik, R Ubar, V Govind
12th IEEE European Test Symposium (ETS'07), 29-34, 2007
Parallel X-fault simulation with critical path tracing technique
R Ubar, S Devadze, J Raik, A Jutman
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Turbo Tester: a CAD system for teaching digital test
G Jervan, A Markus, P Paomets, J Raik, R Ubar
Microelectronics Education, 287-290, 1998
Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source).-Information Science Reference, Hershey
R Ubar, J Raik, HT Vierhaus
SSBDDs: Advantageous model and efficient algorithms for digital circuit modeling, simulation & test
A Jutman, J Raik, R Ubar
Proc. of 5th International Workshop on Boolean Problems (IWSBP'02), 19-20, 2002
Testing strategies for networks on chip
R Ubar, J Raik
Networks on chip, 131-152, 2003
Back-tracing and event-driven techniques in high-level simulation with decision diagrams
R Ubar, J Raik, A Morawiec
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 208-211, 2000
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips
J Raik, V Govind, R Ubar
IET computers & digital techniques 3 (5), 476-486, 2009
Sequential circuit test generation using decision diagram models
J Raik, R Ubar
Proceedings of the conference on Design, automation and test in Europe, 145-es, 1999
Feasibility of structurally synthesized BDD models for test generation
J Raik, R Ubar
Proc. of the IEEE European Test Workshop, 145-146, 1998
Turbo Tester–diagnostic package for research and training
M Aarna, E Ivask, A Jutman, E Orasson, J Raik, R Ubar, V Vislogubov, ...
Радиоэлектроника и информатика, 69-73, 2003
Defect-oriented fault simulation and test generation in digital circuits
W Kuzmicz, W Pleskacz, J Raik, R Ubar
Proceedings of the IEEE 2001. 2nd International Symposium on Quality …, 2001
Hierarchical test generation for combinational circuits with real defects coverage
T Cibakova, M Fischerová, E Gramatová, W Kuzmicz, WA Pleskacz, ...
Microelectronics Reliability 42 (7), 1141-1149, 2002
Internet-based Collaborative Test Generation with MOSCITO
A Schneider, E Ivask, P Miklos, J Raik, KH Diener, R Ubar, T Cibáková, ...
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
Hierarchical defect-oriented fault simulation for digital circuits
M Blyzniuk, T Cibakova, E Gramatova, W Kuzmicz, M Lobur, W Pleskacz, ...
Proceedings IEEE European Test Workshop, 69-74, 2000
Hierarchical identification of NBTI-critical gates in nanoscale logic
S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti
Test Workshop-LATW, 2014 15th Latin American, 1-6, 2014
Structurally synthesized binary decision diagrams
A Jutman, A Peder, J Raik, M Tombak, R Ubar
6th International Workshop on Boolean Problems, 271-278, 2004
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