| A low-voltage low-power voltage reference based on subthreshold MOSFETs G Giustolisi, G Palumbo, M Criscione, F Cutri IEEE Journal of Solid-State Circuits 38 (1), 151-154, 2003 | 422 | 2003 |
| Charge pump circuits: An overview on design strategies and topologies G Palumbo, D Pappalardo IEEE Circuits and Systems Magazine 10 (1), 31-45, 2010 | 407 | 2010 |
| Analysis and comparison on full adder block in submicron technology M Alioto, G Palumbo IEEE transactions on very large scale integration (VLSI) systems 10 (6), 806-823, 2002 | 310 | 2002 |
| Charge-pump circuits: Power-consumption optimization G Palumbo, D Pappalardo, M Gaibotti IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2002 | 264 | 2002 |
| Understanding the effect of process variations on the delay of static and domino logic M Alioto, G Palumbo, M Pennisi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (5), 697-710, 2009 | 229 | 2009 |
| Feedback amplifiers: theory and design G Palumbo, S Pennisi Springer Science & Business Media, 2002 | 217 | 2002 |
| Advances in reversed nested Miller compensation AD Grasso, G Palumbo, S Pennisi IEEE Transactions on Circuits and Systems I: Regular Papers 54 (7), 1459-1470, 2007 | 204 | 2007 |
| Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits M Alioto, G Palumbo Springer Science & Business Media, 2006 | 195 | 2006 |
| Design methodology and advances in nested-Miller compensation G Palumbo, S Pennisi IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2002 | 175 | 2002 |
| Design procedure for two-stage CMOS transconductance operational amplifiers: A tutorial G Palmisano, G Palumbo, S Pennisi Analog Integrated Circuits and Signal Processing 27, 179-189, 2001 | 172 | 2001 |
| CMOS current amplifiers G Palmisano, G Palumbo, S Pennisi Springer Science & Business Media, 1999 | 161 | 1999 |
| A compensation strategy for two-stage CMOS opamps based on current buffer G Palmisano, G Palumbo IEEE transactions on circuits and systems I: fundamental theory and …, 1997 | 147 | 1997 |
| Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies M Alioto, E Consoli, G Palumbo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 725-736, 2010 | 145 | 2010 |
| Design guidelines for reversed nested Miller compensation in three-stage amplifiers R Mita, G Palumbo, S Pennisi IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2003 | 136 | 2003 |
| Design strategies for source coupled logic gates M Alioto, G Palumbo IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2003 | 131 | 2003 |
| General strategies to design nanometer flip-flops in the energy-delay space M Alioto, E Consoli, G Palumbo IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1583-1596, 2009 | 127 | 2009 |
| Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part II—Results and figures of merit M Alioto, E Consoli, G Palumbo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 737-750, 2010 | 113 | 2010 |
| Variable stage charge pump D Pappalardo, M Gaibotti, G Palumbo, A Conte, SL Giudice US Patent 6,927,441, 2005 | 112 | 2005 |
| Conditional push-pull pulsed latches with 726fJ· ps energy-delay product in 65nm CMOS E Consoli, M Alioto, G Palumbo, J Rabaey 2012 IEEE International Solid-State Circuits Conference, 482-484, 2012 | 105 | 2012 |
| Design procedures for three-stage CMOS OTAs with nested-Miller compensation SO Cannizzaro, AD Grasso, R Mita, G Palumbo, S Pennisi IEEE Transactions on Circuits and Systems I: Regular Papers 54 (5), 933-940, 2007 | 104 | 2007 |
