| On the efficacy of input vector control to mitigate NBTI effects and leakage power Y Wang, X Chen, W Wang, V Balakrishnan, Y Cao, Y Xie, H Yang 2009 10th International Symposium on Quality Electronic Design, 19-26, 2009 | 89 | 2009 |
| Leakage power and circuit aging cooptimization by gate replacement techniques Y Wang, X Chen, W Wang, Y Cao, Y Xie, H Yang Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1-14, 2010 | 73 | 2010 |
| NICSLU: An adaptive sparse matrix solver for parallel circuit simulation X Chen, Y Wang, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 71 | 2013 |
| GPU-accelerated sparse LU factorization for circuit simulation with performance modeling X Chen, L Ren, Y Wang, H Yang IEEE Transactions on Parallel and Distributed Systems 26 (3), 786-795, 2015 | 70 | 2015 |
| A deep learning approach for blind drift calibration of sensor networks Y Wang, A Yang, X Chen, P Wang, Y Wang, H Yang IEEE Sensors Journal 17 (13), 4158-4171, 2017 | 63 | 2017 |
| Computing with ferroelectric FETs: Devices, models, systems, and applications A Aziz, ET Breyer, A Chen, X Chen, S Datta, SK Gupta, M Hoffmann, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 62 | 2018 |
| An escheduler-based data dependence analysis and task scheduling for parallel circuit simulation X Chen, W Wu, Y Wang, H Yu, H Yang IEEE Transactions on Circuits and Systems II: Express Briefs 58 (10), 702-706, 2011 | 57 | 2011 |
| Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits X Yin, X Chen, M Niemier, XS Hu IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018 | 54 | 2018 |
| Blind drift calibration of sensor networks using sparse Bayesian learning Y Wang, A Yang, Z Li, X Chen, P Wang, H Yang IEEE Sensors Journal 16 (16), 6249-6260, 2016 | 43 | 2016 |
| Sparse LU factorization for parallel circuit simulation on GPU L Ren, X Chen, Y Wang, C Zhang, H Yang Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 1125-1130, 2012 | 43 | 2012 |
| Hardware trojan detection in third-party digital intellectual property cores by multilevel feature analysis X Chen, Q Liu, S Yao, J Wang, Q Xu, Y Wang, Y Liu, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 40 | 2017 |
| Design and optimization of FeFET-based crossbars for binary convolution neural networks X Chen, X Yin, M Niemier, XS Hu Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 39 | 2018 |
| Run-time technique for simultaneous aging and power optimization in GPGPUs X Chen, Y Wang, Y Liang, Y Xie, H Yang Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, 1-6, 2014 | 39 | 2014 |
| Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification Y Cai, Y Lin, L Xia, X Chen, S Han, Y Wang, H Yang Proceedings of the 55th Annual Design Automation Conference, 107, 2018 | 33 | 2018 |
| FASTrust: Feature analysis for third-party IP trust verification S Yao, X Chen, J Zhang, Q Liu, J Wang, Q Xu, Y Wang, H Yang Test Conference (ITC), 2015 IEEE International, 1-10, 2015 | 33 | 2015 |
| An adaptive LU factorization algorithm for parallel circuit simulation X Chen, Y Wang, H Yang Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012 | 32 | 2012 |
| Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation X Chen, L Wang, B Li, Y Wang, X Li, Y Liu, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 31 | 2016 |
| A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms X Chen, L Wang, Y Wang, Y Liu, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 29 | 2017 |
| Variation-aware supply voltage assignment for simultaneous power and aging optimization X Chen, Y Wang, Y Cao, Y Ma, H Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (11 …, 2012 | 28 | 2012 |
| FPGA accelerated parallel sparse matrix factorization for circuit simulations W Wu, Y Shan, X Chen, Y Wang, H Yang Reconfigurable Computing: Architectures, Tools and Applications, 302-315, 2011 | 28 | 2011 |
Yu Wang(汪玉)Department of Electronic Engineering, Tsinghua University, ChinaZweryfikowany adres z mail.tsinghua.edu.cn
