| A CMOS bandgap reference circuit with sub-1-V operation H Banba, H Shiga, A Umezawa, T Miyaba, T Tanzawa, S Atsumi, K Sakui IEEE Journal of Solid-State Circuits 34 (5), 670-674, 1999 | 1268 | 1999 |
| Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state T Endoh, Y Tanaka, S Aritome, R Shirota, S Shuto, T Tanaka, G Hemink, ... US Patent 5,774,397, 1998 | 674 | 1998 |
| A dynamic analysis of the Dickson charge pump circuit T Tanzawa, T Tanaka IEEE Journal of solid-state circuits 32 (8), 1231-1240, 1997 | 518 | 1997 |
| A multipage cell architecture for high-speed programming multilevel NAND flash memories K Takeuchi, T Tanaka, T Tanzawa IEEE Journal of Solid-State Circuits 33 (8), 1228-1238, 1998 | 234 | 1998 |
| Circuit techniques for a 1.8-V-only NAND flash memory T Tanzawa, T Tanaka, K Takeuchi, H Nakamura IEEE Journal of Solid-State Circuits 37 (1), 84-89, 2002 | 165 | 2002 |
| Non-volatile semiconductor memory device T Endoh, Y Tanaka, S Aritome, R Shirota, S Shuto, T Tanaka, G Hemink, ... US Patent 5,555,204, 1996 | 147 | 1996 |
| 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory T Tanaka, M Helm, T Vali, R Ghodsi, K Kawai, JK Park, S Yamada, F Pan, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 142-144, 2016 | 141 | 2016 |
| Nonvolatile semiconductor memory device capable of controlling mutual timing of write voltage pulse and transfer voltage pulse S Satoh, R Shirota, T Tanzawa US Patent 6,252,798, 2001 | 126 | 2001 |
| Optimization of word-line booster circuits for low-voltage flash memories T Tanzawa, S Atsumi IEEE Journal of Solid-State Circuits 34 (8), 1091-1098, 1999 | 119 | 1999 |
| Semiconductor memory device T Tanaka, H Nakamura, T Tanzawa US Patent 6,525,964, 2003 | 112 | 2003 |
| Non-volatile semiconductor memory device Y Takano, T Taura, T Tanzawa US Patent 6,639,837, 2003 | 108 | 2003 |
| A compact on-chip ECC for low cost flash memories T Tanzawa, T Tanaka, K Takeuchi, R Shirota, S Aritome, H Watanabe, ... IEEE Journal of Solid-State Circuits 32 (5), 662-669, 1997 | 108 | 1997 |
| Method and apparatus for generating temperature-compensated read and verify operations in flash memories T Tanzawa US Patent 7,277,355, 2007 | 102 | 2007 |
| Flash memory T Tanaka, N Shibata, T Tanzawa US Patent 7,219,285, 2007 | 99 | 2007 |
| Flash memory T Tanaka, N Shibata, T Tanzawa US Patent 7,509,566, 2009 | 95 | 2009 |
| Nonvolatile semiconductor memory device T Tanaka, K Ohuchi, T Tanzawa, K Takeuchi US Patent 6,545,909, 2003 | 94 | 2003 |
| Quantum tunneling effect device and semiconductor composite substrate H Watanabe, N Yasuda, A Toriumi, T Tanaka, T Tanzawa US Patent 6,320,220, 2001 | 92 | 2001 |
| Method and apparatus for generating temperature-compensated read and verify operations in flash memories T Tanzawa US Patent 7,957,215, 2011 | 90 | 2011 |
| Non-volatile semiconductor memory device T Endoh, Y Tanaka, S Aritome, R Shirota, S Shuto, T Tanaka, G Hemink, ... US Patent 5,946,231, 1999 | 86 | 1999 |
| Nonvolatile semiconductor memory device T Tanaka, K Ohuchi, T Tanzawa, K Takeuchi US Patent 6,363,010, 2002 | 82 | 2002 |
