| Package systems having interposers WC Wu, SY Hou, S Jeng, CH Yu US Patent 9,048,233, 2015 | 1243 | 2015 |
| Fan-out interconnect structure and method for forming same CH Yu, YC Hu, CW Hsiao, MJ Lii, CS Liu, CL Hwang, CW Lin, CS Chen US Patent 9,368,460, 2016 | 1194 | 2016 |
| Package with metal-insulator-metal capacitor and method of manufacturing the same CH Yu, SY Hou, WC Chiou, JP Hung, DC Yeh, CH Yeh US Patent 9,263,511, 2016 | 1181 | 2016 |
| Stacked semiconductor devices and methods of forming same CH Yu, CH Lee, TD Wang, JW Cheng US Patent 9,496,189, 2016 | 1178 | 2016 |
| Methods of forming integrated circuit package CH Yu, CH Wu, WC Chiou, HF Lee, SP Tai, C Tang-Jung US Patent 9,281,254, 2016 | 1172 | 2016 |
| Testing of semiconductor chips with microbumps WC Wu, HP Hu, SY Hou, S Jeng, CH Yu, CH Yang US Patent 9,372,206, 2016 | 1171 | 2016 |
| Packaging methods and structures using a die attach film JP Hung, JC Lin, LIU Nai-Wei, CC Chang, CH Yu, S Jeng, CF Kao, ... US Patent 9,064,879, 2015 | 1107 | 2015 |
| Methods and apparatus of wafer level package for heterogeneous integration technology CH Yu, DC Yeh US Patent 9,111,949, 2015 | 830 | 2015 |
| 3DIC stacking device and method of manufacture JC Lin, CH Yu US Patent 9,443,783, 2016 | 684 | 2016 |
| Structure and method for 3D IC package SY Hou, DC Yeh, S Jeng, CH Yu US Patent 8,993,380, 2015 | 677 | 2015 |
| Packaging methods and structures for semiconductor devices CW Lin, MD Cheng, LU Wen-Hsiung, HJ Lin, BP Jang, CS Liu, MJ Lii, ... US Patent 8,884,431, 2014 | 637 | 2014 |
| Fin field-effect transistors CH Yu, YR Hsu, CN Yeh US Patent 7,667,271, 2010 | 598 | 2010 |
| Embedded wafer-level bonding approaches CH Yu, JC Lin US Patent 8,361,842, 2013 | 552 | 2013 |
| Interconnect structure for wafer level package CH Yu, JC Lin, LIU Nai-Wei, JP Hung, S Jeng US Patent 8,829,676, 2014 | 544 | 2014 |
| Fan-out package structure and methods for forming the same CH Yu, DC Yeh US Patent 8,803,306, 2014 | 530 | 2014 |
| Packages with passive devices and methods of forming the same CH Yu, SY Hou, DC Yeh, SM Chen, CH Yeh, YJ Lin US Patent 8,680,647, 2014 | 518 | 2014 |
| Method of fabricating a gate dielectric for high-k metal gate devices CH Chang, CH Hou, CH Yu, TB Wu US Patent 9,711,373, 2017 | 471 | 2017 |
| Multi-stack package-on-package structures AJ Su, CH Yu US Patent 9,735,131, 2017 | 436 | 2017 |
| Germanium FinFETs having dielectric punch-through stoppers CH Chang, YR Hsu, CY Lee, ST Hung, CN Yeh, CH Yu US Patent 8,048,723, 2011 | 410 | 2011 |
| Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer CS Liu, CH Yu US Patent 7,858,519, 2010 | 385 | 2010 |
