| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 108 | 2019 |
| Scheduling-context capabilities: A principled, light-weight operating-system mechanism for managing time A Lyons, K McLeod, H Almatary, G Heiser Proceedings of the Thirteenth EuroSys Conference, 1-16, 2018 | 45 | 2018 |
| CompartOS: CHERI compartmentalization for embedded systems H Almatary, M Dodson, J Clarke, P Rugg, I Gomes, M Podhradsky, ... arXiv preprint arXiv:2206.02852, 2022 | 9 | 2022 |
| Reducing the Implementation Overheads of IPCP and DFP H Almatary, NC Audsley, A Burns 2015 IEEE Real-Time Systems Symposium, 295-304, 2015 | 9 | 2015 |
| CHERI Compartmentalisation for Embedded Systems H Almatary University of Cambridge, 2022 | 6 | 2022 |
| Operating system kernels on multi-core architectures H Almatary University of York, 2016 | 3 | 2016 |
| edge (MIPS) Core H AlMatary | 3 | |
| TestRIG: Framework for testing RISC-V processors with Random Instruction Generation J Woodruff, A Joannou, P Rugg, H Xia, J Clarke, H Almatary, P Mundkur, ... | 2 | 2021 |
| Case Study: Securing MMU-less Linux Using CHERI H Almatary, A Mazzinghi, RNM Watson SE 2024-Companion, 69-92, 2024 | | 2024 |
| Experiment Source Code and Raw Data H Almatary, N Audsley, A Burns | | |
