| Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs K Gaj, E Homsirikamol, M Rogawski International Workshop on Cryptographic Hardware and Embedded Systems, 264-278, 2010 | 160 | 2010 |
| ATHENa-automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs K Gaj, JP Kaps, V Amirineni, M Rogawski, E Homsirikamol, BY Brewster 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 109 | 2010 |
| Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs K Gaj, E Homsirikamol, M Rogawski, R Shahid, MU Sharif Cryptology ePrint Archive, 2012 | 97 | 2012 |
| Caesar hardware api E Homsirikamol, W Diehl, A Ferozpuri, F Farahmand, P Yalla, JP Kaps, ... Cryptology ePrint Archive, 2016 | 73 | 2016 |
| Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study E Homsirikamol, K Gaj 2014 International Conference on ReConFigurable Computing and FPGAs …, 2014 | 63 | 2014 |
| Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs E Homsirikamol, M Rogawski, K Gaj International Workshop on Cryptographic Hardware and Embedded Systems, 491-506, 2011 | 57 | 2011 |
| Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs E Homsirikamol, M Rogawski, K Gaj Ecrypt II Hash Workshop 2011, 1-15, 2011 | 47 | 2011 |
| Security margin evaluation of SHA-3 contest finalists through SAT-based attacks E Homsirikamol, P Morawiecki, M Rogawski, M Srebrny Computer Information Systems and Industrial Management: 11th IFIP TC 8 …, 2012 | 42 | 2012 |
| Comprehensive comparison of hardware performance of fourteen round 2 SHA-3 candidates with 512-bit outputs using field programmable gate arrays K Gaj, E Homsirikamol, M Rogawski 2nd SHA-3 Candidate Conference, Santa Barbara, August, 23-24, 2010 | 35 | 2010 |
| Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study E Homsirikamol, KG George 2017 International Conference on Field Programmable Technology (ICFPT), 120-127, 2017 | 29 | 2017 |
| Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates FK Gürkaynak, K Gaj, B Muheim, E Homsirikamol, C Keller, M Rogawski, ... Third SHA-3 Candidate Conference, 1-22, 2012 | 29 | 2012 |
| Hardware api for lightweight cryptography JP Kaps, W Diehl, M Tempelmeier, E Homsirikamol, K Gaj URL https://cryptography. gmu. edu/athena/index. php, 1-26, 2019 | 28 | 2019 |
| A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures A Salman, A Ferozpuri, E Homsirikamol, P Yalla, JP Kaps, K Gaj 2017 international conference on ReConFigurable Computing and FPGAs …, 2017 | 28 | 2017 |
| Implementer’s Guide to Hardware Implementations Compliant with the CAESAR Hardware API E Homsirikamol, P Yalla, F Farahmand, W Diehl, A Ferozpuri, JP Kaps, ... George Mason University, Fairfax, VA, GMU Report, 2016 | 28 | 2016 |
| Gmu hardware api for authenticated ciphers E Homsirikamol, W Diehl, A Ferozpuri, F Farahmand, MU Sharif, K Gaj Cryptology ePrint Archive, 2015 | 26 | 2015 |
| ICEPOLE: high-speed, hardware-oriented authenticated encryption P Morawiecki, K Gaj, E Homsirikamol, K Matusiewicz, J Pieprzyk, ... Cryptographic Hardware and Embedded Systems–CHES 2014: 16th International …, 2014 | 26 | 2014 |
| Hardware benchmarking of cryptographic algorithms using high-level synthesis tools: The SHA-3 contest case study E Homsirikamol, K Gaj Applied Reconfigurable Computing: 11th International Symposium, ARC 2015 …, 2015 | 25 | 2015 |
| A universal hardware API for authenticated ciphers E Homsirikamol, W Diehl, A Ferozpuri, F Farahmand, MU Sharif, K Gaj 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 18 | 2015 |
| A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs M Rogawski, E Homsirikamol, K Gaj 2014 24th International Conference on Field Programmable Logic and …, 2014 | 17 | 2014 |
| ICEPOLE v1 P Morawiecki, K Gaj, E Homsirikamol, K Matusiewicz, J Pieprzyk, ... Submission to CAESAR competition, 2014 | 14 | 2014 |
Kris GajGeorge Mason UniversityVerified email at gmu.edu
