Itir Akgun
Itir Akgun
Zweryfikowany adres z ece.ucsb.edu
Cytowane przez
Cytowane przez
Alleviating irregularity in graph analytics acceleration: A hardware/software co-design approach
M Yan, X Hu, S Li, A Basak, H Li, X Ma, I Akgun, Y Feng, P Gu, L Deng, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5 D/3D integration
D Stow, I Akgun, R Barnes, P Gu, Y Xie
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes
M Poremba, I Akgun, J Yin, O Kayiran, Y Xie, GH Loh
Proceedings of the 44th Annual International Symposium on Computer …, 2017
Scalable memory fabric for silicon interposer-based multi-core systems
I Akgun, J Zhan, Y Wang, Y Xie
2016 IEEE 34th International Conference on Computer Design (ICCD), 33-40, 2016
A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers
J Zhan, I Akgun, J Zhao, A Davis, P Faraboschi, Y Wang, Y Xie
Proceedings of the 49th ACM/IEEE International Symposum on Microarchitecture …, 2016
Cost and thermal analysis of high-performance 2.5 D and 3D integrated circuit design space
D Stow, I Akgun, R Barnes, P Gu, Y Xie
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 637-642, 2016
Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory
AO Glova, I Akgun, S Li, X Hu, Y Xie
Design, Automation, and Test in Europe (DATE), 2019
Efficient system architecture in the era of monolithic 3D: Dynamic inter-tier interconnect and processing-in-memory
D Stow, I Akgun, W Huangfu, Y Xie, X Li, GH Loh
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019
Network-on-chip design guidelines for monolithic 3-D integration
I Akgun, D Stow, Y Xie
IEEE Micro 39 (6), 46-53, 2019
Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems
D Stow, I Akgun, Y Xie
Proceedings of the 21st ACM/IEEE System Level Interconnect Prediction Workshop, 2019
Adaptive multi-level checkpointing
C Xu, I Akgun, P Faraboschi
US Patent 10,769,017, 2020
Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators
M Yan, X Hu, S Li, I Akgun, H Li, X Ma, L Deng, X Ye, Z Zhang, D Fan, ...
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2019
Adaptive multi-level checkpointing
C Xu, I Akgun, P Faraboschi
Lawrence Livermore National Lab.(LLNL), Livermore, CA (United States), 2020
Interconnect Architecture Design for Emerging Integration Technologies
I Akgun
University of California, Santa Barbara, 2020
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