| A cloud-scale acceleration architecture AM Caulfield, ES Chung, A Putnam, H Angepat, J Fowers, M Haselman, ... 2016 49th Annual IEEE/ACM international symposium on microarchitecture …, 2016 | 897 | 2016 |
| Azure accelerated networking:{SmartNICs} in the public cloud D Firestone, A Putnam, S Mundkur, D Chiou, A Dabagh, M Andrewartha, ... 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2018 | 765 | 2018 |
| Serving dnns in real time at datacenter scale with project brainwave E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ... iEEE Micro 38 (2), 8-20, 2018 | 399 | 2018 |
| Fpga-accelerated simulation technologies (fast): Fast, full-system, cycle-accurate simulators D Chiou, D Sunwoo, J Kim, NA Patil, W Reinhart, DE Johnson, J Keefe, ... 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 260 | 2007 |
| An fpga-based in-line accelerator for memcached M Lavasani, H Angepat, D Chiou IEEE Computer architecture letters 13 (2), 57-60, 2013 | 123 | 2013 |
| Configurable clouds AM Caulfield, ES Chung, A Putnam, H Angepat, D Firestone, J Fowers, ... IEEE Micro 37 (3), 52-61, 2017 | 53 | 2017 |
| FPGA-accelerated simulation of computer systems H Angepat, D Chiou, ES Chung, JC Hoe Morgan & Claypool Publishers, 2014 | 35 | 2014 |
| Accurate functional-first multicore simulators D Chiou, H Angepat, N Patil, D Sunwoo IEEE Computer Architecture Letters 8 (2), 64-67, 2009 | 35 | 2009 |
| NIFD: Non-intrusive FPGA Debugger--Debugging FPGA'Threads' for Rapid HW/SW Systems Prototyping H Angepat, G Eads, C Craik, D Chiou 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 28 | 2010 |
| Parallelizing computer system simulators D Chiou, D Sunwoo, H Angepat, J Kim, NA Patil, W Reinhart, DE Johnson 2008 IEEE International Symposium on Parallel and Distributed Processing, 1-5, 2008 | 15 | 2008 |
| Hgum: Messaging framework for hardware accelerators S Zhang, H Angepat, D Chiou 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 11 | 2017 |
| Agile Co-Design for a Reconfigurable Datacenter S Alkalay, H Angepat, A Caulfield, E Chung, O Firestein, M Haselman, ... Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 3 | 2016 |
| Lessons from Implementing a FAST Prototype D Chiou, D Sunwoo, N Patil, J Kim, B Reinhart, H Angepat, DE Johnson 3rd Workshop on Architectural Research Prototyping (WARP’08), Beijing, China, 2008 | 2 | 2008 |
| Telemetry generation for in-field hardware testing JK Oshins, H Angepat US Patent 11,397,656, 2022 | 1 | 2022 |
| Hgum: Messaging framework for hardware accelerators (abstact only) S Zhang, H Angepat, D Chiou Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 1 | 2016 |
| HLS: High-level synthesis for highlevel simulation using FPGAs V Koyyalagunta, H Angepat, D Chiou | 1 | 2010 |
| Embedded Java benchmark analysis on the ARM processor C Isen, H Angepat, LK John, CJ Pil, HJ Song International Journal of Embedded Systems 4 (1), 40-53, 2009 | 1 | 2009 |
| Memory buffer management on hardware devices utilizing distributed decentralized memory buffer monitoring Y Yuan, N Ravichandran, R Groza Jr, Y Yankilevich, HD Angepat US Patent App. 18/600,150, 2024 | | 2024 |
| Telemetry generation for in-field hardware testing JK Oshins, H Angepat US Patent App. 18/538,882, 2024 | | 2024 |
| Memory buffer management on hardware devices utilizing distributed decentralized memory buffer monitoring Y Yuan, N Ravichandran, R Groza Jr, Y Yankilevich, HD Angepat US Patent 11,947,802, 2024 | | 2024 |
Eric S ChungVP of AI Computing, NVIDIAZweryfikowany adres z nvidia.com
