| A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth Y Choi, I Song, MH Park, H Chung, S Chang, B Cho, J Kim, Y Oh, D Kwon, ... 2012 IEEE International Solid-State Circuits Conference, 46-48, 2012 | 451 | 2012 |
| A fully associative, tagless DRAM cache Y Lee, J Kim, H Jang, H Yang, J Kim, J Jeong, JW Lee ACM SIGARCH computer architecture news 43 (3S), 211-222, 2015 | 131 | 2015 |
| A 58nm 1.8 v 1gb pram with 6.4 mb/s program bw H Chung, BH Jeong, BJ Min, Y Choi, BH Cho, J Shin, J Kim, J Sunwoo, ... 2011 IEEE International Solid-State Circuits Conference, 500-502, 2011 | 109 | 2011 |
| Nonvolatile memory device comprising one-time-programmable lock bit register YJ Lee, KJ Lee, JM Park, HW Seo US Patent 8,547,724, 2013 | 80 | 2013 |
| Method of equalizing bit error rates of memory device EC Oh, M Kim, YS Kim, YJ Lee, JH Lee US Patent 11,126,497, 2021 | 65 | 2021 |
| Efficient footprint caching for tagless dram caches H Jang, Y Lee, J Kim, Y Kim, J Kim, J Jeong, JW Lee 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 55 | 2016 |
| Memory devices, memory systems and methods of operating memory devices YJ Lee, TH Na, CO Lim US Patent 10,629,286, 2020 | 46 | 2020 |
| eDRAM-based tiered-reliability memory with applications to low-power frame buffers K Cho, Y Lee, YH Oh, G Hwang, JW Lee Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 35 | 2014 |
| Variable resistance memory device and system Q Wang, KJ Lee, WY Cho, TS Kim, KH Kim, HH Choi, YJ Lee, H Kim US Patent 8,194,492, 2012 | 11 | 2012 |
| Semiconductor device having resistance based memory array, method of reading, and systems associated therewith KJ Lee, DE Kim, YJ Lee US Patent 7,920,432, 2011 | 11 | 2011 |
| Nonvolatile memory and a nonvolatile memory system Y Lee US Patent 10,031,702, 2018 | 7 | 2018 |
| Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation K Hyo-Jin, H Chung, CH Kim, K Yong-Jin, P Eun-Hye, YJ Lee US Patent 9,135,994, 2015 | 5 | 2015 |
| Memory device for generating a compensation current based on a difference between a first read voltage and a second read voltage and a method of operating the same CO Lim, TH Na, J Sunwoo, YJ Lee US Patent 10,580,488, 2020 | 4 | 2020 |
| Memory device having resistance change material and operating method for the memory device CO Lim, HK Park, J Sunwoo, YH Oh, YJ Lee US Patent 10,074,426, 2018 | 4 | 2018 |
| Semiconductor device having resistance based memory array, method of reading, and systems associated therewith KJ Lee, DE Kim, YJ Lee US Patent 8,482,994, 2013 | 4 | 2013 |
| Semiconductor device having resistance based memory array, method of operation, and systems associated therewith YJ Lee, KJ Lee, TS Kim, KH Kim, WY Cho, HH Choi, HJ Kim US Patent 8,218,379, 2012 | 4 | 2012 |
| DRAM architecture for efficient data lifetime management Y Lee, Y Kim, J Jeong, JW Lee ieice electronics express 14 (10), 20170309-20170309, 2017 | 3 | 2017 |
| Nonvolatile memory device and method for controlling word line or bit line thereof JY Choi, B Choi, YH Ro, YJ Lee US Patent 8,305,806, 2012 | 3 | 2012 |
| Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation YJ Lee, BG Choi, DE Kim US Patent 8,254,159, 2012 | 3 | 2012 |
| Method of preventing coupling noises for a non-volatile semiconductor memory device KJ Lee, YJ Lee, DE Kim, WY Cho, JY Choi US Patent 8,102,704, 2012 | 2 | 2012 |
