Ishwar Bhati
Ishwar Bhati
Intel Labs; Oracle; University of Maryland; IITG
Zweryfikowany adres z umd.edu - Strona główna
Cytowane przez
Cytowane przez
DRAM refresh mechanisms, penalties, and trade-offs
I Bhati, MT Chang, Z Chishti, SL Lu, B Jacob
IEEE Transactions on Computers 65 (1), 108-121, 2015
Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions
I Bhati, Z Chishti, SL Lu, B Jacob
Proceedings of the 42nd Annual International Symposium on Computer …, 2015
Techniques to reduce memory cell refreshes for a memory device
ZA Chishti, IS Bhati, SLL Lu
US Patent 9,418,723, 2016
Density tradeoffs of non-volatile memory as a replacement for SRAM based last level cache
K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling
I Bhati, Z Chishti, B Jacob
International Symposium on Low Power Electronics and Design (ISLPED), 205-210, 2013
An integrated simulation infrastructure for the entire memory hierarchy: Cache, dram, nonvolatile memory, and disk
J Stevens, P Tschirhart, MT Chang, I Bhati, P Enns, J Greensky, Z Chisti, ...
Intel Technology Journal 17 (1), 184-200, 2013
Coordinating power mode switching and refresh operations in a memory device
ZA Chishti, I Bhati
US Patent 9,001,608, 2015
Overcoming interconnect scaling challenges using novel process and design solutions to improve both high-speed and low-power computing modes
K Vaidyanathan, DH Morris, UE Avci, IS Bhati, L Subramanian, J Gaur, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.1. 1-20.1. 4, 2017
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein …
IS Bhati, H Liu, J Gaur, K Korgaonkar, S Manipatruni, S Subramoney, ...
US Patent 10,331,582, 2019
Scalable and energy efficient DRAM refresh techniques
IS Bhati
University of Maryland, College Park, 2014
Method and apparatus for reducing write congestion in non-volatile memory based last level caches
KK Korgaonkar, IS Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
US Patent App. 15/475,197, 2018
A journaled, NAND-flash main-memory system
B Jacob, I Bhati, MT Chang, P Rosenfeld, J Stevens, P Tschirhart, ...
Electrical and Computer Engineering Dept., Systems and Computer Architecture …, 2010
Memory aware reordered source
IS Bhati, U Dhawan, J Gaur, S Subramoney
US Patent 10,866,902, 2020
To cache or to bypass? A fine balance in the emerging memory technology era
K Korgaonkar, I Bhati, H Liu, J Gaur, S Manipatruni, S Subramoney, ...
NVM, 2019
MARS: Memory Aware Reordered Source
I Bhati, U Dhawan, J Gaur, S Subramoney, H Wang
arXiv preprint arXiv:1808.03518, 2018
2016 Index IEEE Transactions on Computers Vol. 65
N Abbas, EAH Abdulrahman, N Abu-Ghazaleh, M Abusultan, O Acevedo, ...
Networks 315, 321, 2016
Producing Reliable Full-System Simulation Results: A Case Study of CMP with Very Large Caches
MT Chang, I Bhati, J Stevens, P Tschirhart, P Enns, D Gerzhoy, Z Chishti, ...
Das, Subhasis, 349 Devadas, Srinivas, 616 Dijk, Marten van, 616 Dreslinksi, Ronald G., 27, 629
Z Du, J Ahn, JH Ahn, H Ahn, B Akin, O Allam, J Alsop, L Alvarez, ...
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