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Rozalia Beica
Rozalia Beica
CTO at Yole Developpement
Verified email at yole.fr
Title
Cited by
Cited by
Year
Through silicon via copper electrodeposition for 3D integration
R Beica, C Sharbono, T Ritzdorf
2008 58th Electronic Components and Technology Conference, 577-583, 2008
1442008
Warpage and thermal characterization of fan-out wafer-level packaging
JH Lau, M Li, D Tian, N Fan, E Kuah, W Kai, M Li, J Hao, YM Cheung, Z Li, ...
IEEE transactions on components, packaging and manufacturing technology 7 …, 2017
1392017
Design, materials, process, fabrication, and reliability of fan-out wafer-level packaging
JH Lau, M Li, QM Li, I Xu, T Chen, Z Li, KH Tan, QX Yong, Z Cheng, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (6 …, 2018
842018
Fan-out wafer-level packaging for heterogeneous integration
JH Lau, M Li, ML Qingqian, T Chen, I Xu, QX Yong, Z Cheng, N Fan, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (9 …, 2018
812018
Advanced metallization for 3D integration
R Beica, P Siblerud, C Sharbono, M Bernt
2008 10th Electronics Packaging Technology Conference, 212-218, 2008
632008
Chip-first fan-out panel-level packaging for heterogeneous integration
CT Ko, H Yang, JH Lau, M Li, M Li, C Lin, JW Lin, T Chen, I Xu, CL Chang, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 8 (9 …, 2018
562018
Warpage measurements and characterizations of fan-out wafer-level packaging with large chips and multiple redistributed layers
JH Lau, M Li, L Yang, M Li, I Xu, T Chen, S Chen, QX Yong, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 8 …, 2018
542018
Through-silicon-via technology for 3D integration
J Dukovic, S Ramaswami, S Pamarthy, R Yalamanchili, N Rajagopalan, ...
2010 IEEE International Memory Workshop, 1-2, 2010
392010
Electroplating compositions and methods
R Beica, ND Brown, K Wang
US Patent 7,151,049, 2006
322006
Copper electrodeposition for 3D integration
R Beica, C Sharbono, T Ritzdorf
2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 127-131, 2008
312008
3D integration: Applications and market trends
R Beica
2015 International 3D Systems Integration Conference (3DIC), TS5. 1.1-TS5. 1.7, 2015
282015
Design, materials, process, and fabrication of fan-out panel-level heterogeneous integration
CT Ko, H Yang, J Lau, M Li, M Li, C Lin, JW Lin, CL Chang, JY Pan, ...
Journal of Microelectronics and Electronic Packaging 15 (4), 141-147, 2018
252018
Reliability of fan-out wafer-level packaging with large chips and multiple re-distributed layers
J Lau, M Li, L Yang, M Li, QX Yong, Z Cheng, T Chen, I Xu, N Fan, E Kuah, ...
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 1574-1582, 2018
222018
3D technology applications market trends & key challenges
A Pizzagalli, T Buisson, R Beica
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014 …, 2014
192014
Reliability of fan-out wafer-level heterogeneous integration
J Lau, M Li, Y Lei, M Li, I Xu, T Chen, QX Yong, Z Cheng, W Kai, P Lo, Z Li, ...
International Symposium on Microelectronics 2018 (1), 000224-000232, 2018
182018
Flip chip market and technology trends
R Beica
2013 Eurpoean Microelectronics Packaging Conference (EMPC), 1-4, 2013
182013
Control of breakdown products in electroplating baths
LA Gomez, R Beica, D Morrissey, EN Step
US Patent 6,508,924, 2003
162003
Seed layer recovery
D Morrissey, J Calvert, R Beica
US Patent App. 09/977,596, 2002
162002
Seed layer recovery
D Morrissey, J Calvert, R Beica
US Patent App. 09/977,596, 2002
162002
Soft gold electroplating from a non-cyanide bath for electronic applications
K Wang, R Beica, N Brown
IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology …, 2004
132004
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