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Alessandro Ottaviano
Alessandro Ottaviano
PhD student, ETH Zurich
Verified email at iis.ee.ethz.ch
Title
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Cited by
Year
Cheshire: A lightweight, linux-capable risc-v host platform for domain-specific accelerator plug-in
A Ottaviano, T Benz, P Scheffler, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
72023
A high-performance, energy-efficient modular DMA engine architecture
T Benz, M Rogenmoser, P Scheffler, S Riedel, A Ottaviano, A Kurth, ...
IEEE Transactions on Computers, 2023
62023
ControlPULP: a RISC-V power controller for HPC processors with parallel control-law computation acceleration
A Ottaviano, R Balas, G Bambini, C Bonfanti, S Benatti, D Rossi, L Benini, ...
International Conference on Embedded Computer Systems, 120-135, 2022
42022
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
A Ottaviano, R Balas, G Bambini, A Del Vecchio, M Ciani, D Rossi, ...
International Journal of Parallel Programming, 1-31, 2024
22024
Yun: An open-source, 64-bit RISC-V-Based vector processor with multi-precision integer and floating-point support in 65-nm CMOS
M Perotti, M Cavalcante, A Ottaviano, J Liu, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
22023
Towards a RISC-V Open Platform for Next-generation Automotive ECUs
L Cuomo, C Scordino, A Ottaviano, N Wistoff, R Balas, L Benini, E Guidieri, ...
2023 12th Mediterranean Conference on Embedded Computing (MECO), 1-8, 2023
22023
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
R Balas, A Ottaviano, L Benini
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024
2024
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
S Riedel, M Gantenbein, A Ottaviano, T Hoefler, L Benini
arXiv preprint arXiv:2401.09359, 2024
2024
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
A Ottaviano, R Balas, P Sauter, M Eggimann, L Benini
arXiv preprint arXiv:2311.09645, 2023
2023
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs
T Benz, A Ottaviano, R Balas, A Garofalo, F Restuccia, A Biondi, L Benini
arXiv preprint arXiv:2311.09662, 2023
2023
Adversarial Machine Learning against Real-World Attacks on CNN Object Detectors
A Ottaviano
Politecnico di Torino, 2020
2020
D5. 4 Evaluation of the operating systems and hypervisors
JR SYS, IMS EVI, CS EVI, LC EVI, T Cucinotta, G Ara, A Ottaviano, ...
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