Synthesis of arithmetic circuits: FPGA, ASIC and embedded systems JP Deschamps, GJA Bioul, GD Sutter John Wiley & Sons, 2006 | 310 | 2006 |
Hardware implementation of finite-field arithmetic JP Deschamps McGraw-Hill, Inc., 2009 | 201 | 2009 |
Efficient elliptic curve point multiplication using digit-serial binary field operations GD Sutter, JP Deschamps, JL Imaña IEEE Transactions on Industrial Electronics 60 (1), 217-225, 2012 | 189 | 2012 |
Modular multiplication and exponentiation architectures for fast RSA cryptosystem based on digit serial computation GD Sutter, JP Deschamps, JL Imana IEEE Transactions on industrial electronics 58 (7), 3101-3109, 2010 | 103 | 2010 |
Guide to FPGA implementation of arithmetic functions JP Deschamps, GD Sutter, E Cantó Springer Science & Business Media, 2012 | 83 | 2012 |
Limago: An FPGA-based open-source 100 GbE TCP/IP stack M Ruiz, D Sidler, G Sutter, G Alonso, S López-Buedo 2019 29th International Conference on Field Programmable Logic and …, 2019 | 79 | 2019 |
Low-power FSMs in FPGA: Encoding alternatives G Sutter, E Todorovich, S López-Buedo, E Boemo Integrated Circuit Design. Power and Timing Modeling, Optimization and …, 2002 | 62 | 2002 |
FPGA implementations of BCD multipliers G Sutter, E Todorovich, G Bioul, M Vazquez, JP Deschamps 2009 International Conference on Reconfigurable Computing and FPGAs, 36-41, 2009 | 46 | 2009 |
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture I Gonzalez, S Lopez-Buedo, G Sutter, D Sanchez-Roman, ... Journal of Systems Architecture 58 (6-7), 247-256, 2012 | 34 | 2012 |
High speed fixed point dividers for FPGAs G Sutter, JP Deschamps 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 34 | 2009 |
Experiments in low power FPGA design G Sutter, E Boemo Latin American applied research 37 (1), 99-104, 2007 | 32 | 2007 |
Decimal addition in FPGA G Bioul, M Vazquez, JP Deschamps, G Sutter 2009 5th Southern Conference on Programmable Logic (SPL), 101-108, 2009 | 27 | 2009 |
FSM decomposition for low power in FPGA G Sutter, E Todorovich, S Lopez-Buedo, E Boemo Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 26 | 2002 |
Comparative study of SRT-dividers in FPGA G Sutter, G Bioul, JP Deschamps International Conference on Field Programmable Logic and Applications, 209-220, 2004 | 25 | 2004 |
Bridging the gap between hardware and software open source network developments M Forconesi, G Sutter, S Lopez-Buedo, JEL de Vergara, J Aracil IEEE Network 28 (5), 13-19, 2014 | 22 | 2014 |
Decimal adders/subtractors in FPGA: efficient 6-input LUT implementations M Vazquez, G Sutter, G Bioul, JP Deschamps 2009 International Conference on Reconfigurable Computing and FPGAs, 42-47, 2009 | 21 | 2009 |
Hardware implementation of finite-field division JP Deschamps, G Sutter Acta Applicandae Mathematica 93, 119-147, 2006 | 21 | 2006 |
Power aware dividers in FPGA G Sutter, JP Deschamps, G Bioul, E Boemo Integrated Circuit and System Design. Power and Timing Modeling …, 2004 | 21 | 2004 |
A tool for activity estimation in FPGAs E Todorovich, M Gilabert, G Sutter, S López-Buedo, E Boemo Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002 | 21 | 2002 |
Decimal division: Algorithms and FPGA implementations JP Deschamps, G Sutter 2010 VI Southern Programmable Logic Conference (SPL), 67-72, 2010 | 20 | 2010 |