| MemPool: A shared-L1 memory many-core cluster with a low-latency Interconnect M Cavalcante, S Riedel, A Pullini, L Benini 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 701-706, 2021 | 31 | 2021 |
| Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters M Cavalcante, D Wüthrich, M Perotti, S Riedel, L Benini Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 11 | 2022 |
| Banshee: A Fast LLVM-Based RISC-V Binary Translator S Riedel, F Schuiki, P Scheffler, F Zaruba, L Benini 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 8 | 2021 |
| ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor A Kurth, S Riedel, F Zaruba, T Hoefler, L Benini 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 7 | 2020 |
| A high-performance, energy-efficient modular DMA engine architecture T Benz, M Rogenmoser, P Scheffler, S Riedel, A Ottaviano, A Kurth, ... IEEE Transactions on Computers, 2023 | 6 | 2023 |
| MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory S Riedel, M Cavalcante, R Andri, L Benini IEEE Transactions on Computers 72 (12), 3561-3575, 2023 | 6 | 2023 |
| Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs A Agnesina, M Brunion, A Garcia-Ortiz, F Catthoor, D Milojevic, ... Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2022 | 6 | 2022 |
| MemPool-3D: boosting performance and efficiency of shared-l1 memory many-core clusters with 3D integration M Cavalcante, A Agnesina, S Riedel, M Brunion, A García-Ortiz, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 394-399, 2022 | 6 | 2022 |
| ISA extensions in the Snitch Processor for Signal Processing L Benini, A Macii, S Riedel, M Cavalcante, S Mazzola | 4* | |
| MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster S Riedel, GH Khov, S Mazzola, M Cavalcante, R Andri, L Benini 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2023 | 2 | 2023 |
| Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster M Bertuletti, S Riedel, Y Zhang, A Vanelli-Coralli, L Benini International Conference on Embedded Computer Systems, 241-254, 2023 | 1 | 2023 |
| Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters S Mazzola, S Riedel, L Benini arXiv preprint arXiv:2402.12986, 2024 | | 2024 |
| LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation S Riedel, M Gantenbein, A Ottaviano, T Hoefler, L Benini arXiv preprint arXiv:2401.09359, 2024 | | 2024 |
| Hier-3D: A Methodology for Physical Hierarchy Exploration of 3D ICs NE Bethur, A Agnesina, M Brunion, A Garcia-Ortiz, F Catthoor, D Milojevic, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | | 2023 |
| Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster A Vanelli-Coralli, L Benini Embedded Computer Systems: Architectures, Modeling, and Simulation: 23rd …, 2023 | | 2023 |
| MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS S Riedel, M Cavalcante, M Frouzakis, D Wüthrich, E Mustafa, A Billa, ... 2023 30th IEEE International Conference on Electronics, Circuits and Systems …, 2023 | | 2023 |
| Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency M Cavalcante, M Perotti, S Riedel, L Benini arXiv preprint arXiv:2309.10137, 2023 | | 2023 |
| Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters M De Araujo Cavalcante, D Wüthrich, M Perotti, S Riedel, L Benini 41th IEEE/ACM International Conference on Computer Aided Design (ICCAD 2022), 2022 | | 2022 |
