PowerSynth: A power module layout generation tool TM Evans, Q Le, S Mukherjee, I Al Razi, T Vrotsos, Y Peng, HA Mantooth IEEE Transactions on Power Electronics 34 (6), 5063-5078, 2018 | 73 | 2018 |
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs T Song, C Liu, Y Peng, SK Lim Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013 | 46 | 2013 |
The increasing role of design automation in power electronics: Gathering what is needed K Hermanns, Y Peng, A Mantooth IEEE Power Electronics Magazine 7 (1), 46-50, 2020 | 45 | 2020 |
Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling Y Peng, T Song, D Petranovic, SK Lim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 43 | 2014 |
PowerSynth design automation flow for hierarchical and heterogeneous 2.5-D multichip power modules I Al Razi, Q Le, TM Evans, S Mukherjee, HA Mantooth, Y Peng IEEE Transactions on Power Electronics 36 (8), 8919-8933, 2021 | 42 | 2021 |
On enhancing power benefits in 3D ICs: Block folding and bonding styles perspective M Jung, T Song, Y Wan, Y Peng, SK Lim Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 37 | 2014 |
Full-chip signal integrity analysis and optimization of 3-D ICs T Song, C Liu, Y Peng, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 30 | 2015 |
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs Y Peng, T Song, D Petranovic, SK Lim 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 281-288, 2013 | 26 | 2013 |
Chiplet-package co-design for 2.5 D systems using standard ASIC CAD tools MDA Kabir, Y Peng 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 351-356, 2020 | 21 | 2020 |
Powersynth 2: Physical design automation for high-density 3-d multichip power modules I Al Razi, Q Le, TM Evans, HA Mantooth, Y Peng IEEE Transactions on Power Electronics 38 (4), 4698-4713, 2023 | 19 | 2023 |
PEEC method and hierarchical approach towards 3D multichip power module (MCPM) layout optimization Q Le, T Evans, Y Peng, HA Mantooth 2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), 131-136, 2019 | 19 | 2019 |
Toward partial discharge reduction by corner correction in power module layouts S Mukherjee, T Evans, B Narayanasamy, Q Le, AI Emon, A Deshpande, ... 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics …, 2018 | 19 | 2018 |
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM Y Peng, BW Ku, Y Park, KI Park, SJ Jang, JS Choi, SK Lim Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 18 | 2015 |
Electronic design automation (EDA) tools and considerations for electro-thermo-mechanical co-design of high voltage power modules TM Evans, S Mukherjee, Y Peng, HA Mantooth 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 5046-5052, 2020 | 16 | 2020 |
Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs) Q Le, T Evans, S Mukherjee, Y Peng, T Vrotsos, HA Mantooth 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA …, 2017 | 16 | 2017 |
Design methodologies for low-power 3-D ICs with advanced tier partitioning M Jung, T Song, Y Peng, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017 | 15 | 2017 |
Constraint-Aware Algorithms for Heterogeneous Power Module Layout Synthesis and Reliability Optimization I Al Razi, Q Le, HA Mantooth, Y Peng 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA …, 2018 | 14 | 2018 |
Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses Q Le, I Al Razi, TM Evans, S Mukherjee, Y Peng, HA Mantooth IEEE Journal of Emerging and Selected Topics in Power Electronics, 2023 | 12 | 2023 |
Design challenges of intra-and inter-chiplet interconnection C Chen, J Yin, Y Peng, M Palesi, W Cao, L Huang, AK Singh, H Zhi, ... IEEE Design and Test 39 (6), 99-109, 2022 | 12 | 2022 |
Ultralow power circuit design with subthreshold/near-threshold 3-D IC technologies SK Samal, Y Peng, M Pathak, SK Lim IEEE Transactions on Components, Packaging and Manufacturing Technology 5 (7 …, 2015 | 11 | 2015 |