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Eojin Lee
Tytuł
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TWiCe: Preventing Row-hammering by Exploiting Time Window Counters
E Lee, I Kang, S Lee, GE Suh, JH Ahn
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
482019
Graphene: Strong yet Lightweight Row Hammer Protection
Y Park, W Kwon, E Lee, TJ Ham, JH Ahn, JW Lee
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
242020
TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering
E Lee, S Lee, GE Suh, JH Ahn
IEEE Computer Architecture Letters 17 (1), 96-99, 2018
212018
CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention
I Kang, E Lee, JH Ahn
IEEE Access 8, 17366-17377, 2020
142020
Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology: Industrial Product
S Lee, S Kang, J Lee, H Kim, E Lee, S Seo, H Yoon, S Lee, K Lim, H Shin, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
132021
TRiM: Tensor Reduction in Memory
B Kim, J Park, E Lee, M Rhu, JH Ahn
IEEE Computer Architecture Letters 20 (1), 5-8, 2020
102020
TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory
J Park, B Kim, S Yun, E Lee, M Rhu, JH Ahn
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
62021
MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks
B Kim, J Chung, E Lee, W Jung, S Lee, J Choi, J Park, M Wi, S Lee, ...
IEEE Transactions on Computers 69 (7), 955-967, 2020
62020
Accelerating Fully Homomorphic Encryption Through Architecture-Centric Analysis and Optimization
W Jung, E Lee, S Kim, J Kim, N Kim, K Lee, C Min, JH Cheon, JH Ahn
IEEE Access 9, 98772-98789, 2021
52021
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent
H Kim, H Park, T Kim, K Cho, E Lee, S Ryu, HJ Lee, K Choi, J Lee
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
42021
SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures
Y Ro, H Cho, E Lee, D Jung, YH Son, JH Ahn, JW Lee
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
42017
Work as a team or individual: Characterizing the system-level impacts of main memory partitioning
E Lee, J Chung, D Jung, S Lee, S Li, JH Ahn
2017 IEEE International Symposium on Workload Characterization (IISWC), 156-166, 2017
32017
Semiconductor memory device employing processing in memory (PIM) and operation method of the semiconductor memory device
S Seo, B Kim, J Park, J Ahn, WI Minbok, S Lee, LEE Eojin, J Wonkyung, ...
US Patent 11,139,033, 2021
12021
MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation framework
DJ Oh, Y Moon, E Lee, TJ Ham, Y Park, JW Lee, JH Ahn
Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on …, 2021
12021
Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture
Y Ro, E Lee, J Ahn
Electronics 7 (8), 130, 2018
12018
Reset-in-set: improving PCM write throughput by reducing the peak power of multi-bit writes
Y Ro, E Lee, JH Ahn
Electronics Letters 51 (17), 1320-1322, 2015
12015
An FPGA-based RNN-T Inference Accelerator with PIM-HBM
S Kang, S Lee, B Kim, H Kim, K Sohn, NS Kim, E Lee
Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022
2022
MaPHeA: A Framework for Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation
DJ Oh, Y Moon, DK Ham, TJ Ham, Y Park, JW Lee, JH Ahn, E Lee
ACM Transactions on Embedded Computing Systems (TECS), 2022
2022
Semiconductor memory device employing processing in memory (pim) and operation method of the semiconductor memory device
S Seo, B Kim, J Park, J Ahn, WI Minbok, S Lee, LEE Eojin, J Wonkyung, ...
US Patent App. 17/462,298, 2021
2021
Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module
LEE Eojin, K Ingab, JH Ahn
US Patent 11,037,618, 2021
2021
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