Obserwuj
Lasse Natvig
Tytuł
Cytowane przez
Cytowane przez
Rok
Experimental validation of the learning effect for a pedagogical game on computer fundamentals
G Sindre, L Natvig, M Jahre
IEEE Transactions on Education 52 (1), 10-18, 2008
942008
A cache-partitioning aware replacement policy for chip multiprocessors
H Dybdahl, P Stenström, L Natvig
High Performance Computing-HiPC 2006: 13th International Conference …, 2006
672006
An lru-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches
H Dybdahl, P Stenström, L Natvig
ACM SIGARCH Computer Architecture News 35 (4), 45-52, 2007
642007
Age of computers: game-based teaching of computer fundamentals
L Natvig, S Line
ACM SIGCSE Bulletin 36 (3), 107-111, 2004
492004
Towards an intelligent environment for programming multi-core computing systems
S Pllana, S Benkner, E Mehofer, L Natvig, F Xhafa
Euro-Par 2008 Workshops-Parallel Processing: VHPC 2008, UNICORE 2008, HPPC …, 2009
392009
" Age of computers"; an innovative combination of history and computer game elements for teaching computer fundamentals
L Natvig, S Line, A Djupdal
34th Annual Frontiers in Education, 2004. FIE 2004., S2F-1, 2004
382004
ParVec: vectorizing the PARSEC benchmark suite
JM Cebrian, M Jahre, L Natvig
Computing 97 (11), 1077-1100, 2015
332015
Logarithmic time cost optimal parallel sorting is not yet fast in practice!
L Natvig
Conference on High Performance Networking and Computing: Proceedings of the …, 1990
301990
Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks
JM Cebrian, M Jahre, L Natvig
2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014
282014
Storage efficient hardware prefetching using delta-correlating prediction tables
M Grannaes, M Jahre, L Natvig
Journal of Instruction-Level Parallelism 13, 1-16, 2011
272011
Scalability analysis of AVX-512 extensions
JM Cebrian, L Natvig, M Jahre
The Journal of supercomputing 76 (3), 2082-2097, 2020
252020
High-level architectural simulation of the torus routing chip
L Natvig
Proceedings of Meeting on Verilog HDL (IVC/VIUF'97), 48-55, 1997
251997
A light-weight fairness mechanism for chip multiprocessor memory systems
M Jahre, L Natvig
Proceedings of the 6th ACM conference on Computing frontiers, 1-10, 2009
242009
Performance and energy impact of parallelization and vectorization techniques in modern microprocessors
JM Cebrián, L Natvig, JC Meyer
Computing 96 (12), 1179-1193, 2014
232014
Improving energy efficiency through parallelization and vectorization on intel core i5 and i7 processors
JM Cebrian, L Natvig, JC Meyer
2012 SC Companion: High Performance Computing, Networking Storage and …, 2012
232012
Cost-comfort balancing in a smart residential building with bidirectional energy trading
A Al Hasib, N Nikitin, L Natvig
2015 Sustainable Internet and ICT for Sustainability (SustainIT), 1-6, 2015
212015
Case studies of multi-core energy efficiency in task based programs
H Lien, L Natvig, A Al Hasib, JC Meyer
ICT as Key Technology against Global Warming: Second International …, 2012
182012
A high performance adaptive miss handling architecture for chip multiprocessors
M Jahre, L Natvig
Transactions on High-Performance Embedded Architectures and Compilers IV, 1-20, 2011
142011
V-pfordelta: Data compression for energy efficient computation of time series
A Al Hasib, JM Cebrian, L Natvig
2015 IEEE 22nd International Conference on High Performance Computing (HiPC …, 2015
132015
A quantitative study of memory system interference in chip multiprocessor architectures
M Jahre, M Grannaes, L Natvig
2009 11th IEEE International Conference on High Performance Computing and …, 2009
132009
Nie można teraz wykonać tej operacji. Spróbuj ponownie później.
Prace 1–20