| Area–oriented technology mapping for LUT–based logic blocks M Kubica, D Kania International Journal of Applied Mathematics and Computer Science 27 (1 …, 2017 | 55 | 2017 |
| Decomposition of multi-output functions oriented to configurability of logic blocks M Kubica, D Kania Bulletin of the Polish Academy of Sciences-Technical Sciences 65 (3), 317-331, 2017 | 39 | 2017 |
| Logic synthesis for FPGAs based on cutting of BDD M Kubica, A Opara, D Kania Microprocessors and Microsystems 52, 173-187, 2017 | 38 | 2017 |
| Technology mapping oriented to adaptive logic modules M Kubica, D Kania Bulletin of the Polish Academy of Sciences. Technical Sciences 67 (5), 2019 | 33 | 2019 |
| Methods of improving time efficiency of decomposition dedicated at FPGA structures and using BDD in the process of cyber-physical synthesis A Opara, M Kubica, D Kania IEEE Access 7, 20619-20631, 2019 | 30 | 2019 |
| Technology Mapping for LUT-based FPGA M Kubica, A Opara, D Kania Springer, 2021 | 29 | 2021 |
| A technology mapping of FSMs based on a graph of excitations and outputs M Kubica, D Kania, J Kulisz IEEE Access 7, 16123-16131, 2019 | 29 | 2019 |
| SMTBDD: new form of BDD for logic synthesis M Kubica, D Kania International Journal of Electronics and Telecommunications 62 (1), 33--41, 2016 | 28 | 2016 |
| Strategy of logic synthesis using MTBDD dedicated to FPGA A Opara, M Kubica, D Kania Integration 62, 142-158, 2018 | 26 | 2018 |
| SMTBDD: new concept of graph for function decomposition M Kubica, D Kania IFAC-PapersOnLine 48 (4), 49-54, 2015 | 17 | 2015 |
| Decomposition time effectiveness for various synthesis strategies dedicated to FPGA structures M Kubica, D Kania, A Opara AIP Conference Proceedings 1790 (1), 2016 | 12 | 2016 |
| Optimization of synthesis process directed at FPGA circuits with the usage of non-disjoint decomposition A Opara, M Kubica AIP Conference Proceedings 1906 (1), 2017 | 10 | 2017 |
| The choice of decomposition path taking non-disjoint decomposition into account A Opara, M Kubica AIP Conference Proceedings 2040 (1), 2018 | 9 | 2018 |
| Logic synthesis strategy oriented to low power optimization M Kubica, A Opara, D Kania Applied Sciences 11 (19), 8797, 2021 | 8 | 2021 |
| Reconfigurable Logic Controller—Direct FPGA Synthesis Approach A Milik, M Kubica, D Kania Applied Sciences 11 (18), 8515, 2021 | 8 | 2021 |
| Technology mapping of FSM oriented to LUT-based FPGA M Kubica, D Kania Applied Sciences 10 (11), 3926, 2020 | 7 | 2020 |
| Logic synthesis of low power FSM for LUT-based FPGA M Kubica, K Kajstura, D Kania AIP Conference Proceedings 2040 (1), 2018 | 6 | 2018 |
| Decomposition synthesis strategy directed to FPGA with special MTBDD representation A Opara, M Kubica AIP Conference Proceedings 1790 (1), 2016 | 3 | 2016 |
| Synteza logiczna zespołu funkcji ukierunkowana na minimalizację liczby wykorzystywanych bloków logicznych PAL w oparciu o zmodyfikowany graf wyjść M Kubica, D Kania Pomiary Automatyka Kontrola 57 (7), 737-740, 2011 | 3 | 2011 |
| Graph of outputs in the process of synthesis directed at CPLDs M Kubica, D Kania Mathematics 7 (12), 1171, 2019 | 2 | 2019 |
